Adam Garrison wrote:
In my research I was unable to find where only LPUART0 is the boot device. Section 13.4.3 of the K27 TRM does not mention that the Boot device is restricted to LPUART0. Can you please direct me to where this assignment to only LPUART0 is mentioned in the TRM?
Also, in the case of the MKL17Z256VFM4 (32 QFN) the LPUART0 two locations in the pinmap.
For example LPUART0_RX can be on pin 11 or 31, likewise LPUART0_TX can be on pin 12 or 32.
Am I obliged to use a particular RX/TX pair or does the ROM bootloader check both?
I second this query. I'm looking at the reference manual for the KL17 (KL17P64M48SF6RM.pdf), and one would be hard-pressed to say definitively which SPI, I2C, and LPUART pins are active within the bootloader. In fact, there would seem to be conflicting information. From page 185, section 13.2.9, Bootloader Exit State, detailing which registers and peripherals are not returned to their default state after a bootloader operation:
Affected pin mux:
• UART1(PTE0, PTE1)
• I2C1(PTC10, PTC11)
• SPI1(PTD4, PTD5, PTD6, PTD7)
But this is from page 190, section 13.3.3, LPUART Peripheral:
Autobaud feature: If LPUARTn is used to connect to the bootloader, then the LPUARTn_RX (PTA1) pin must be kept high and not left floating during the detection phase in order to comply with the autobaud detection algorithm.
So, Freescale, which is it? I'm pretty sure from other forum posts I've read that it's LPUART0 on PTA1/2 that's used for the bootloader. And if someone wanted to use I2C to bootload the device, can we be sure it's PTC10/11? Those pins aren't even available on the 32-pin and 48-pin parts, only the 64-pin package. It would be extremely useful if you would update your documentation and make it clear which communication pins are active for a given Kinetis device in the bootloader.
