DSPI MOSI configuration K82 - Set idle level low?

[JorgeLC]

Hi everyone, thanks beforehand for your help.

I am developing a project in a MK82FN256VLL15 microcontroller, with which I communicate via DualSPI with an external BLE module.

Using the default "fsl_dspi" driver library, I can send the desired messages from the controller as a master without issue. However, I have seen that the messages are sent with an active low setting, and I would like to change it to active high.

I have looked for different configuration options within the initialization functions of the library:

- "void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz)"

- "void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig)"
and I have been able to configure the CLK active level (masterConfig->ctarConfig.cpol) and the ChipSelect level (DSPI_SetOnePcsPolarity)

I am also trying to change the idle level of the MOSI line from high (default) to low, to run a couple of specific tests, but I cant seem to find how to do so.

Does this possibility even exist by firmware? Or would I need to invert the bit by bit values in the middle of the MOSI line?

Once again, thanks a lot!

[xiangjun_rong · Accepted solution]

Hi,

When the SPI is configured as master, the MOSI(master output slave in) line is data output pin, the pin can not be set or cleared by software, it is determined by data you transfer.

For example, if the 16 bits data 0xAAAA is transferred, the MOSI will be High, Low,High, Low...with the SCK assume the MSB is transmitted first, during the transfer idle or the /CS is deasserted, the MOSI is high impedance, you can connect an external  pull up or down resistor to get high or low logic.

Hope it can help you

BR

XiangJun Rong

[JorgeLC]

Hi,

Thanks a lot for your answer! It definitely helped.
I will tackle the base logic level with an external resistor then.

BR
Jorge