Hello MARK,
About the clock, yes, you can see the clock diagram:

About the core clock, flash clock, flexbus clock ext. The gate is in the SIM module, you can use the SIM register to control the OUTDIV and gate.
Yes, SIM_SCGC6[0] is the flash clock gate enable bit.
SIM_SCGC7 bits [3] is the SDRAMC clock gate control, and bit [0] is the flexbus clock gate control.
Diagram is the sketch map, the details register, you still need to check SIM chapter, normally, different module have different clock gate.
Core and bus is the chip main clock, so it doesn't have the SIM gate, you just need to control the OUTDIV, this is the divider.
chapter 7.3.4 item 2 is not very correct for MK26, this description is just copied from for other normal kinetis which don't have the gate, you can ignore it, but must make sure the according clock gate is enabled, actually, after reset, the flash clock is enabled in default, even you don't configure it, it still can be used, but when you use the sdram and the flexbus, you must enable it by yourself in the SIM registser.
When you do the code configuration, you totally can refer to our SDK sample code, that code has been tested.
Wish it helps you!
Have a great day,
Kerry
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