AHB-AP auto address increment overflow in KE04z64

[andrewparlane2]

I'm writing code to program a KE04z64 over SWD and am running into a few issues with the TAR register wrapping when auto increment single mode is enabled.

The ARM Debug Interface v5 doc says that auto increment is only guaranteed to operate on the bottom 10 bits of the TAR register, any more than that is implementation defined. (Specified in ARM Debug Interface v5 (IH0031A) section 8.2.2 under the Increment Single heading.

However I can't find any docs that say what this is for the KE04z64 (using the cortex m0+ core). For the K66 (using the cortex m4 core) Section 8.2.2 shows the CSW register bits, under the "Address" field, it states that the increment wraps at a 4KB boundary (so it operates on the bottom 12 bits).

I've looked in all documents I can find relating to the cortex m0+ but I just can't find any reference to this.

Any ideas.

Andrew

[andrewparlane2 · Accepted solution]

I've finally located this, it's in the coresight SOC TRM (which I thought I'd checked). There is a 1KB boundary which matches observed behaviour.