NXP's Bug in arch.h header file for EPWM's fault interrupt register's offset value (MC56F83xx)

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NXP's Bug in arch.h header file for EPWM's fault interrupt register's offset value (MC56F83xx)

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fasihahmed
Contributor IV

Hey,

Background:

I am porting my legacy code from DSC MC56F827xx to new DSC MC56F83xx.

One such is to port the same GCT's configurations to new PWM_A_ FaultCh1 module.

However I never receive a PWM fault interrupt when I have external faults occurring via linked GPIO pins. Although the same configurations work fine on old DSC.

fasihahmed_0-1610056100963.png

 

register pictures.PNG

Problem:

Further investigation reveals that there may be a possible bug in the new DSC's "arch.h" stand alone application code.

There is a mismatch between datasheet's PWM_A_FCTRL1 offset position to what is defined in the "arch.h"  source code. 

Please see the picture of attached data sheet and source code which reveals that they don't match their offset values. (Datasheet's register value CCh instead of source code's CAh).

We have tried to fix this by placing a dummy register to compensate for the missing register variable.

Can you verify this bug and suggest its possible solution?

pwm settings.PNG

 

@xiangjun_rong 

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2 Replies

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johanpaul
Contributor I

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johanpaul
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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Fasih,

I think you are right. The eFlexPWM register address of MC56F83xxx has changed from that of MC56F827xx, but the arch.h has not changed accordingly.

I will contact the quickStart team for modification.

BR

XiangJun Rong

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