bit DONE and BCR register in DMA

[vale]

Hallo,

I've just finished developing a simple program where 32 bytes are transferred from UART to a buffer through a DMA channel on my M52235EVB board.

When transfer is completed, the DMA channel sends an interrupt which is served by an ISR.

In the ISR I'd like to reconfigure the DMA to transfer 32 bytes more.

Hence I reload the BCR register with the number 32,

then clear the interrupt writing 1 to the bit DONE in DSR to allow DMA to restart the transfer.

The problem is that writing 1 to the bit DONE seems to reset the BCR register, preventing DMA to restart the transfer.

The solution seems to be to write the bit DONE BEFORE loading the BCR register with the number 32.

I don't like very much this solution: if a byte has arrived to the UART when I've already set the DONE bit but before BCR register is reloaded, I'll get a configuration error on DMA....

What is a better solution?

Can anyone help?

Valentina

[mccPaul]

Hi Valentina,

I haven't used the DMA with a UART before and I don't think that I follow exactly what you are doing. The UART FIFO only has three bytes that can be read by the DMA so I haven't been able to work out how you get a 32 byte transfer.

The manual (section 26.4.6.1.2) says that the DMA transfers from the UARTs should be set up for cycle steal mode and 1 byte transfers; it also says that a typical application will use RXRDY, not FFULL to make the DMA request. It seems to me that this may overcome the problem with resetting the BCR count because the DMA transfer is forced to 1 byte in CS mode (see table 20-4).

Cheers,

Paul.

[vale]

Hi Paul,

if the UART is receiving a byte stream it will request a DMA channel everytime the RXRDY flag is set.

For example, if you transfer 32 byte to the UART, the RXRDY flag will be set 32 times.

If properly configured (CS=1), each time the RXRDY flag gets set, the DMA will get the byte from the UART RX buffer and move it to the destination specified in DAR register.

This transfer will be repeated for 32 times as long as you have written this number in the BCR register of DMA.

For each transfer, the BCR value will be decreased of one unity: after 32 transfers it will reach value 0.

As soon as this happens, you will have 32 bytes in the destination specified in DAR register.

My problem is that I have to repeat these 32 bytes transfer. Hence I must reload value 32 in BCR and set DONE bit to 1 to have the transfer restart.

Setting DONE bit to 1 deletes value 32 in BCR, hence I have to write BCR register after bit DONE.

The problem is that if some bytes arrive to the UART between these two instructions, DMA may originate a configuration error because a DMA request is active with BCR still loaded with value zero.

Valentina

[mccPaul]

Ok, that makes sense now.

The solution is to stop the UART from generating DMA requests before you set the DMA done flag. Can you do this by changing the routing in the DMAREQC register? If there is no route available for the UISRn:RXRDY flag to initiate a DMA request then you should be able to reconfigure the DMA controller without a confilct occuring. When the DMA is reconfigured, you can reset the route in DMAREQC and if any characters are in the UART rx buffer a DMA request will be generated immediately.

Cheers,

Paul.

[vale]

Hallo Paul,

thank you for your suggestion.

I reset the route in DMAREQC before reconfiguring DMA, then I set it again and it seems to work.

Anyway I'm going to post a new request on the Forum to get an example of an ISR serving a DMA interrupt, as I am not sure I have made it correctly.

Thank you

Valentina