MCF5223X do not start watchdog

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MCF5223X do not start watchdog

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gxd
Contributor I
same as  Paynete' s problem :
 
 
Working with ColdFire_Lite Tcp Stack.  Having an issue with unresponsive TCP or general lockup.  Thought I would enable watchdog.
 
Changed mcf5223_wtm_init in mcf5223_sysinit.c to turn on Watchdog.
void mcf5223_wtm_init(void)
{
 /*
 * Enable Software Watchdog Timer - Timing 2^23 * Bus Freq
 */
 MCF_SCM_CWCR =  MCF_SCM_CWCR_CWT(5)  |
     MCF_SCM_CWCR_CWE  |
     MCF_SCM_CWCR_CWTA  |
     MCF_SCM_CWCR_CWTAVAL |
     MCF_SCM_CWCR_CWTIC  ;
           
 MCF_INTC0_ICR8  =  MCF_INTC_ICR_IL(2);     
 MCF_INTC0_IMRL &= ~(MCF_INTC_IMRL_MASK8);
  
 MCF_SCM_CWSR = 0x55;
 MCF_SCM_CWSR = 0xAA;
}
 
Tried without setting    CWTA,  CWTAVAL,  & CWTIC  also.
 
Added _watchdog_handler to mcf5223_vectors.s as .extern and to vector48:
 .extern _watchdog_handler
vector48: .long  _watchdog_handler //_irq_handler
 
Added  watchdog_handler to Int_handlers.c to perform soft reset
__interrupt__
void watchdog_handler (void)
{
  mcf5xxx_irq_disable();
 MCF_CIM_RCR |= MCF_CIM_RCR_SOFTRST;  //TEP Software Reset *********************** 
}
 
Purposely did not service the CWSR on a periodic basis for test.
 

 
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421 次查看
gxd
Contributor I
Thank your help!
 
i solve the problem by first set the mask_all bit(clear) ,then (after do so)set the intc0_imrl_mask.
if i first set intc0, then set the mask_all bit(clear). it can not work.
i can not know why freescale do not explani it clearly. but other interrupt not need so(in this order).
 
hope it is useful for all people.
 
God help us!


Message Edited by gxd on 2008-06-16 01:58 AM
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bkatt
Contributor IV
MCF_SCM_CWCR has a "feature" that it can only be written once after each reset. So if your debugger or some init code writes a zero to it before your attempt to enable it, the enable will not work. You can check if it is enabled by (MCF_SCM_CWCR & MCF_SCM_CWCR_CWE).

Here we use MCF_INTC0_ICR8 = MCF_INTC_ICR_IL(7) to make the interrupt non-maskable. While we can deliberately avoid servicing the CWSR to verify that the watchdog works under "normal" conditions, the chip can still get into states where it does not work, and we don't know why...

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SimonMarsden_de
Contributor II
Are other interrupts working OK? If not, here are a couple of suggestions:

(a) Have you cleared the MASKALL bit in the IMRL register?

     MCF_INTC0_IMRL &= ~MCF_INTC_IMRL_MASKALL;

(b) Have you dropped the interrupt fence in the processor's main status register (SR)? The processor boots with the value 0x2700 in the SR, which means that the fence is 7 and all interrupts are masked. To set the fence to 0, try something like

    asm_set_ipl(0);


Hope this helps


Simon
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