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Hi,
I need to perform a read from serial flash. I did a single byte write. After that, I am trying to do a read from the same address location. Opcode+3 address bytes are send first.
Buff[0] = 0x03; /* opcode for read */
Buff[1] = 0x00; /* first address byte*/
Buff[2] = 0x01; /* middle address byte*/
Buff[3] = 0x00; /* last address byte*/
write (fp, Buff, 4);
Then a call to
read (fp, &Buf, 1);
is made.
When I check with oscilloscope, I find that after the opcode +3 address bytes have been send the chip select becomes high and then becomes low for the clock cycle for read. The read command is returning 0x00 always. As per actual requirement, the chip select should continuously remain low until the read is over.
What could be the problem here? The transfer mode is QSPI_TRANSFER_MODE_3. The CSIVbit in QWR is zero. During the write operation, the CS was remaining low throughout.
Thanks,
Chen
> the chip select should continuously remain low until the read is over.
For the CS remain asserted between the transfers, set CONT bit of each QCR entry to 1.
Hi,
One more thing to add,
the read () call return 1 - the number of bytes read - which is correct.
But the value read is always 0x00.
Thanks,
Chen