MCF5307? That's an old one. The User Manual (Rev 2.0) is dated August 2000. That's a good thing as it should be a lot simpler than the later ones, with less things to go wrong (in setup, configuration, booting etc).
> I am trying to help a whole community of people who have problems with this synth.
I could read that as a community, all of whom use one single synth, but I assume you mean there's a lot of people with a lot of these things, all over a decade old, and all showing similar problems. If that's the case, check all the power supplies with an oscilloscope. The electrolytic capacitors dry out in these things and that usually puts ripple on some of the power supplies. That may be dropping low enough to trigger whatever is used for the power-on-reset. Given it is a Synth with analog outputs, there should be other power supplies for the analog side. Make sure none of them have ripples and are upsetting some other circuitry and generating lots of interrupts or something.
This CPU is so simple it only has two power supplies - VCC, which is 3.3V and PVCC for the PLL. Later models have all sorts of different lower core voltages. Check those supplies for level and ripple. Make sure the capacitor on the PVCC supply hasn't dried out or shorted. or something.
You HAVE to use an Oscilloscope. You can't do this properly with a multimeter.
Make sure the JTAG pins aren't at the wrong levels. That can force the CPU into a debug mode. Make sure TRST, TMS and TDI are at the proper levels, or pulled to the correct supplies as per Chapter 19. Check HIZ.
The only other important inputs for the CPU are the RSTIN and Clock Input (CLKIN) from an external oscillator. Make sure the input clock is OK and the right frequency. it is possible that crystals may get damaged, "wear out" or suffer voltage drift. Read the PLL chapter to see what multipliers the CPU is set to apply. There should be pullup or pulldown resistors on Data Bus Pins D0-D7 (or perhaps a tri-state buffer enabled by RSTIN or RSTOUT) that set the initial clock frequencies and other bus parameters like the bus width. See 17.5.5. If these are wrong the CPU won't boot. If the board has jumpers or switches to allow some of these parameters to be changed, then maybe the jumpers or switches are corroded, a jumper has fallen off or someone has fiddled with them.
RSTOUT should follow RSTIN as per the diagram in 7.4.2, as long as the clock is OK.
BCLKO is "compulsory". That one should be toggling. The PSTCLK signal is only required if you are debugging, and being a high frequency clock it is often a problem for EMC Emissions. So it is normal to turn this one OFF. That is done in code by the "CSR[PCD]" bit and register, see Figure and Table 5.8. Then notice an 18 year old BUG in the manual, where "PCD is listed in the Table, but is missing from the Figure, so you don't know what its reset value is!
Fortunately there's an Errata for the manual. Unfortunately it doesn't fix this bug. Looking in manuals for later chips (like the MCF5329) shows the Figure properly filled in and showing the initial value of "zero". So PSTCLK should be toggling after reset, but the chip may execute some code that turns it off later - if it gets that far.
Assuming all that is working, watch the chip select signals. The CPU starts executing by fetching locations 0 and 4 in main memory and then jumping to the start vector. The Chip Select Module defaults to enabling CS0 for all accesses until programmed otherwise. So CS0 should be toggling. If the code runs from ROM/FLASH, then it should keep toggling. If the system loads the code from FLASH into RAM and runs it from there, then CS0 may only run for a a fraction of a second before one of the other chip selects (connected to RAM) takes over.
Make sure nothing is pulling the BR (Bus Request) signal down or the CPU will give up the bus.
If it is getting that far and going off the rails, make sure nothing is doing something stupid on any of the interrupt request lines.
Tom