The CW .cfg files are incorrect. CPLD access needs wait-states and setup/hold delays. The correct values are below (with some added comments). This fixed the problem...
;Init CS0 - Flash0 @ 0x0400_0000
; CSAR0 = 0x0400 Base Address
; CSMR0 = 8*64k Blocks, VALID
; CSCR0 = 4 W/S, Auto-Ack, 8-Bit
writemem.l 0xFC008000 0x04000000;
writemem.l 0xFC008008 0x00001140;
writemem.l 0xFC008004 0x00070001;
;Init CS1 - Flash1 @ 0x0000_0000
; CSAR0 = 0x0000 Base Address
; CSMR0 = 512*64k Blocks, VALID
; CSCR0 = 3 W/S, Auto-Ack, 8-Bit, Byte-Enable
writemem.l 0xFC00800C 0x00000000;
writemem.l 0xFC008014 0x00000D60;
writemem.l 0xFC008010 0x01FF0001;
;Init CS2 - CPLD @ 0x0800_0000
; CSAR0 = 0x0800 Base Address
; CSMR0 = 8*64k Blocks, VALID
; CSCR0 = Address Setup Delay = 4, R/W Address Hold = 4, 4 W/S, Auto-Ack, 8-Bit
writemem.l 0xFC008018 0x08000000;
writemem.l 0xFC008020 0x003F1140;
writemem.l 0xFC00801C 0x00070001;
;Init CS3 - FPGA @ 0x0900_0000
; CSAR0 = 0x0800 Base Address
; CSMR0 = 8*64k Blocks, VALID
; CSCR0 = 32-Bit, Byte-Enable
writemem.l 0xFC008024 0x09000000;
writemem.l 0xFC00802C 0x00000020;
writemem.l 0xFC008028 0x00070001;