5475 branch cache causing instruction fetch from invalid memory

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5475 branch cache causing instruction fetch from invalid memory

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KenJohnson
Contributor II
My 5475 system has no memory mapped at 0x00000000. If I invalidate and then configure data, instruction, and branch caches, the following code (with full optimization) causes an instruction fetch from address 0x00000000 (which causes an XLB Arbiter timeout.) If the branch cache is not enabled, no instruction fetch from address 0x00000000 occurs:

------ example code ------
typedef void (*tFuncPtr)(void);
void f1( void ){
return;
}

tFuncPtr ftable[]={
f1,f1,(tFuncPtr)0
};

void Test( void )
{
tFuncPtr s, *p;

if (!(p = ftable)) return;

for ( ; (s = *p) != 0; p++)
s();
}

------ end example code ------

Is there any way to prevent the branch cache from fetching instructions from invalid memory?

The CACR and ACRs are configured as follows on my 5475 system:

CACR = 0x84088400
ACR0 = 0x601C0020
ACR1 = 0x7007C400
ACR2 = 0x6001C000
ACR3 = 0x9001C000

Thanks,

Ken
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659 次查看
cote
Contributor I
Ken,

Please refer to device errata #32 (see link below) which *might* be root cause of the extra i-fetch you're seeing with branch cache enabled. I say *might* because I'd have to see the exact assembly code sequence to be sure. If the issue is not related to device errata #32, then please post the exact assembly sequence for further assistance.

http://www.freescale.com/files/32bit/doc/errata/MCF5475DE.pdf?fsrch=1
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KenJohnson
Contributor II
I don't believe this issue is related to Device Errata #32 since the TRAPF instruction is not contained in the assembly. The assembly for the Test() function follows. If the branch cache is enabled and ftable contains at least two valid function pointers (I used f1 for this test followed by a null pointer to terminate the list, an instruction fetch from 0 will occur on the last pass through the loop.

typedef void (*tFuncPtr)(void);
void f1( void ){
return;
}

tFuncPtr ftable[]={
f1,f1,(tFuncPtr)0
};


; 312: void Test( void )
;
; 313: {
; 314: tFuncPtr s, *p;
; 315:
;
0x00000000 0x4E560000 link a6,#0
0x00000004 0x2F0D move.l a5,-(a7)
;
;
; 316: if (!(p = ftable)) return;
; 317:
; 318: for ( ; (s = *p) != 0; p++)
;
0x00000006 0x4BF900000000 lea _ftable,a5
0x0000000C 0x4A8D tst.l a5
0x0000000E 0x6608 bne.s *+10 ; 0x00000018
0x00000010 0x600C bra.s *+14 ; 0x0000001e
;
;
; 319: s();
;
0x00000012 0x4E90 jsr (a0)
0x00000014 0x4BED0004 lea 4(a5),a5
0x00000018 0x2055 movea.l (a5),a0
0x0000001A 0x4A88 tst.l a0
0x0000001C 0x66F4 bne.s *-10 ; 0x00000012
0x0000001E 0x2A5F movea.l (a7)+,a5
0x00000020 0x4E5E unlk a6
0x00000022 0x4E75 rts
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meteorcool
Contributor I
It seems that I ran into the same problem. I don't think the branch cache problem is related to the TPF instruction too.
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