Privilege violation ColdFire 5329

[ebsec]

Hello,

I want to use a PIT interruption with a Coldfire 5329.

When the interruption occurs, there is an error "Privilege violation".

Does someone help me?

Thanks

Eric

Message Edited by J2MEJediMaster on 2007-04-19 10:58 AM

[J2MEJediMaster]

Looking at the source code in your window, executing a lot of ANSI library code to print a string while you're in an interrupt handler that's supposed to be lean and fast isn't a good idea. Try just having the handler increment a variable. If you still get the error after that, then how you implemented the interrupt handler code is where the problem lies. But try getting rid of that print() statement first.

---Tom

[ebsec]

I have just insert this printf for debug.

The error persist, the error occurs before executing any code in the interruption.

Where is the problem?

[J2MEJediMaster]

OK, I've studied some Coldfire code, and yes, you should be able to get away with putting a printf() in that interrupt. My mistake. Privilege Violation is itself an interrupt, and the fact that it is appearing when your interrupt fires suggests that the interrupt vectors aren't set up properly. What does your vector table look like?

---Tom

Message Edited by J2MEJediMaster on 2007-04-17 12:23 PM

[ebsec]

Thank you for your help Tom.

Here the initialisation code for the PIT0:

mcf5xxx_irq_disable();
mcf5xxx_set_handler(128+43, PIT0_handler);

/* INTC1 ICR */
MCF_INTC1_ICR(43) =  MCF_INTC_ICR_IL(3);
/* Autorise les its du timer  */
MCF_INTC1_IMRH &= ~(MCF_INTC_IMRH_INT_MASK43);

MCF_PIT0_PMR = 40000;                     // 40MHz/40000 = 1kHz

MCF_PIT0_PCSR = 0                           
                    | MCF_PIT_PCSR_EN        // Bit 0: PIT enable
                    | MCF_PIT_PCSR_RLD     // Bit 1: Counter reloaded from PMRn on count of 0x0000
                    | MCF_PIT_PCSR_PIE       // Bit 3: PIT interrupt enable
                    | MCF_PIT_PCSR_PRE(1); // Bit 8-11: Prescaler 2 (80MHz/2=40MHz)

mcf5xxx_irq_enable();

mcf5xxx_set_handler copy the address of PIT0_handler in the Vector_ram table.

I have make no change in the vector table.

Thanks

Eric

[ebsec]

Now it work correctly with the help of the Freescale Technical Support.

Here the answer i have received:

According to the MCF5329DE errata manual:

The MCF5329 supports the ISA_A+ instruction set. ISA_A+ includes the STLDSR (store load status

register) instruction, but this instruction does not work correctly in the

V3 core.

To eliminite the generation of the STLDSR on your interrupt code with 5329 evb Please add the following line to your interrupt routine declaration:

__declspec(interrupt:0)

void your isr_name(void ) { ... }

Thanks

Eric

[ericgregori]

As a FYI,

This fix does not work on CW 6.4.

CW 6.4 does not correctly remove the instruction from the ISR.

eric.gregori@freescale.com