MC56F8023 I2C does not meet timing

[jnguyen]

Hello,

I tried to contact NXP support for this issue, but they are dreadfully slow at replying.  I hope you guys are better! 

We are having issues with the MC56F8023 doing I2C.  It looks like the SDA is falling at the same time as SCL, resulting in a negative hold time.  Section 10.12 of the spec says that the hold time (tHD; DAT) is at least 0.  If SDA and SCL fall at the same time, that is impossible to be 0 because Figure 10-14 shows that tHD; DAT is defined when SCL is at VIL and SDA is at VIH.  We have looked at the waveforms using an oscilloscope and it shows a negative hold time.  In addition, we've connected the pins to an I2C analyzer and it also affirms that the hold time is negative and it is incorrectly reading data because of this.

I tend to believe that we have something set wrong in CodeWarrior, as I find it hard to believe that NXP/Freescale would so obviously miss something like this and release this chip with a huge flaw.  Where can I set the hold time in CodeWarrior or what are we doing wrong?

Thanks!

[Stano]

Hi J Nguyen,

the simplest way to properly set the internal peripherals in the 56F8023 DSC is to use the QuickStart v.2.63 tool. You can reach it on web:

https://www.nxp.com/webapp/Download?colCode=DSC56800EXQUICKSTARTSW&appType=license&location=null&Par...

Here is the window from this tool:

You can simply set all peripherals and the output is in "appconfig.h" file:

Example for I2C:

/*.

    IIC Configuration

--------------------------------------------

.*/

#define IIC_ENBL_INIT                     0x0001U

#define IIC_CTRL_INIT                     0x0063U

#define IIC_SAR_INIT                      0x0055U

#define IIC_RXFT_INIT                     0x0000U

#define IIC_TXFT_INIT                     0x0000U

#define IIC_SSHCNT_INIT                   0x009BU

#define IIC_SSLCNT_INIT                   0x009CU

#define IIC_FSHCNT_INIT                   0x0023U

#define IIC_FSLCNT_INIT                   0x0024U

#define IIC_IENBL_INIT                    0x08FFU

Best Regards,

Stano.

[jnguyen]

Hi Stano,

Thank you so much for the reply!  I am not sure I understand fully.  There is no direct line showing hold time.  Are you saying that if I adjust the SCL high/low time that the SDA high/low time does not change?  I guess I'm asking if the SDA remains at 50% duty cycle even as the SCL high/low times change?  Otherwise, I don't see how to adjust the hold times in this window.

Thanks!

[Stano · Accepted solution]

Hi J Nguyen,

You can set-up the internal clocks of the I2C module - it is derived from SystemBusClock. This set-up shows you the communication speed on the I2C line. The SDA pin is controlled by the internal I2C module and all timing depends on the I2C internal clock. The internal hardware maintains the proper functionality of the both SCL and SDA pins during communication.

First of all it must be set the values in the SSLCNT and SSHCNT registers. Then the first step in the communication is to change the the MSTEN bit to 1 (the SLVDIS must be =1), then write data into I2C data register. The hold time is automatically set to right value. The SDA line can be changed only while the SCL = 0.

The duty cycle of the SDA line is not a matter. It depends on the set communication speed and I2C line electrical properties. Also it depends on the I2C slave properties.

Best Regards,

Stano.