CW10 P&E simulator and external XTAL clock

[bobelec]

Hello,

I'm using CodeWarrior 10 and its integrated emulator to simulate a MC9S08DZ128 microcontroller.

I would like to lock the chip PLL on an external simulated oscillator (4MHz).

The initialization shown below is running correctly until the wait for PLL lock loop wich is endless : I can't get the PLL to lock on the ext clock.

I'm not using the ProcessorExpert features of CW10 so the only way to enable the external clock simulation and to define its frequency is through the "Change External Clock Frequency" window in the PEMicro menu. I put 4000000 (I guess it's hertz, there's no unit) in this window.

The problem is that the PEMicro menu is greyed until the simulation has started, so I can't set the clock before starting the simulator. At that point the ext clock is "DISABLED" until the first breakpoint at the beginning of the main function where I can manually set the ext clock (too late ?).

Each time I restart the chip I have to redefine the ext clock manually as it's disabled by default. Is there an other way to define this ext chock simulator that I missed ?

Thanks for your help.t

Here's my Init code:

Unfortunately I don't have the harware yet so I couldn't test it on real HW.

Thanks to tell me if that's a code issue or a clock simulator configuration issue.

  SOPT1 = 0x00;                                      
  SOPT2 = 0x00;                                      
  SPMSC1 = 0x00;                                      
  SPMSC2 = 0x00;                                      

  if (*(unsigned char*)0xFFAF != 0xFF) { /* Test if the device trim value is stored on the specified address */
    MCGTRM = *(unsigned char*)0xFFAF;  /* Initialize MCGTRM register from a non volatile memory */
    MCGSC = *(unsigned char*)0xFFAE;   /* Initialize MCGSC register from a non volatile memory */
  }
 
  // Transition from initial FEI mode to FBE mode
  MCGC2 = 0x36;         // MCGC2: BDIV=1 (div by 1),RANGE=1,HGO=1,LP=0,EREFS=1,ERCLKEN=1,EREFSTEN=0

  while( ! MCGSC_OSCINIT ) {              /* Wait until external reference is stable */
       SRS = 0x55;                         /* Reset watchdog counter write 55, AA */
       SRS = 0xAA;
  }

  MCGC3_DIV32 = 1;       // MCGC3: DIV32=1         Setting DIV32 (bit 4) in MCGC3 is strongly recommended for FLL external modes when using a high frequency range (RANGE = 1) external reference clock              
 
  // Entering FBE mode
  MCGC1 = 0x90;         // MCGC1: CLKS=2 (ext. clock),RDIV=2 (div by 128 : 4MHz/128 = 31.25KHz ),IREFS=0,IRCLKEN=0,IREFSTEN=0

  while(MCGSC_IREFST  ) {        // Loop until IREFST is 0, indicating the external reference is the current source for the reference clock
       SRS = 0x55;                         /* Reset watchdog counter write 55, AA */
       SRS = 0xAA;
  }

  // in FBE mode wait until CLKST bits have changed to 2 indicating that external ref clock has been selected
  while(MCGSC_CLKST1 != 1 && MCGSC_CLKST0 != 0) {    //Loop until CLKST is %10, indicating that the external reference clock is selected to feed MCGOUT
       SRS = 0x55;                         /* Reset watchdog counter write 55, AA */
       SRS = 0xAA;
  }
 
//  MCGT = 1; // MCGT_DRST_DRS=1, MCGT_DMX32=0 pour changer ce registre, LP et PLLS doivent être à 0

//  while(MCGSC_LOCK == 0) {        // Wait until PLL is locked on external reference after changing MCGT
//    _FEED_COP();
//  }
 
  // Transition to PBE mode:
  // MCGC3: LOLIE=0,PLLS=1 (PLL is selected),CME=0 (Clock monitor disabled),DIV32=1,VDIV=0x08
  // VDIV (bits 3-0) set to %1000, or multiply-by-32 because 1 MHz reference * 32= 32MHz
  MCGC3 = 0x58;          

  while( ! MCGSC_PLLST ) {        // PBE: Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the PLLS clock is the PLL
   SRS = 0x55;                         /* Reset watchdog counter write 55, AA */
   SRS = 0xAA;
  }

  while( ! MCGSC_LOCK ) {        // Wait until PLL is locked on external reference

// endless loop here
       SRS = 0x55;                         /* Reset watchdog counter write 55, AA */
       SRS = 0xAA;
  }

[bobelec]

Hello,

I reply to myself.

I finally found a way to automatically set the external Xtal frequency at startup of the emulator:

I put "gdi XTAL 4000000t" at the end of my MC9S08DZ128.tcl configuration file (in Project_Settings/Debugger/)

This line set the Xtal frequency to 4MHz and enables the external clock generator. It saves me some mouse clicks at each simulation start.

Concerning the PLL that is not locking, I could lock it but I had to change the Multipurpose Clock Generator initialization sequence.: in page 189 of the datasheet PDF it is recommended to wait for PLL lock (2.e) before changing the MCGC1 register (3.a) to transition from PBE mode to PEE mode. I changed this sequence and wait for PLL lock _after_ changing the MCGC1 register and waiting for the CLKST bits to be %11. This way it works.

Is the datasheet wrong ?