DMA_LDD transfer complete ISR uses wrong user data

[davidnemes]

My Processor Expert K20 project uses Codewarrior for MCU version 10.6.

1.  The DMA_LDD component attached is meant to generate a DMA transfer completion interrupt, for DMA channels 0 and 16. The PE generated code erroneously passes the User Data pointer for DMA channel 0 to the ISR, when it should reference DMA channel 16 instead.

2. The DMA completion interrupt stops after a while if both DREQ and INTMAJOR bits are set in the DMA TCD. However if the DMA is left enabled after transfer completion, the interrupt is never lost.  Could this be caused by a hardware race condition where the disable request stops the interrupt being generated?

3. My application needs a large number of hardware DMA triggers, but the sub family reference manual K20P144M120SF3RM says a trigger source should not be used to trigger more than one DMA channel, as it could cause "unpredictable behaviour". I have tested using one FTM channel to trigger multiple DMA channels and did not find any problems. Exactly what is meant by "unpredictable behaviour" in this case?

Original Attachment has been moved to: DMA1.c.zip

Original Attachment has been moved to: DMA1.h.zip

[Alice_Yang]

Hello David,

Please show your project , and it can clearly see the configuration of PE.

Or it hard to find the problem.

BR

Alice

[davidnemes]

I have attached a cut down project that shows the code generation bug. Thanks.

[davidnemes]

Just to be clear, I am only after a general answer for questions 2 and 3, where 2 was asking when a DMA channel simultaneously disables itself and generates a transfer done interrrupt, is the interrupt request latched or can it be disabled and never generated due to the disabling of the DMA channel?

[Alice_Yang]

Hello David,

1) The channel 0 and channel 16 of DMA hold the same interrupt vector :

You check the register of "DMA_INT" to check the interrupt source is channel 0 or channel 16 .

2) Do you want disable the DMA complete interrupt ? If yes, you can disable it on here :

if not , you can tell me your purpose in detail.

3)About this question , this is the restriction of the hardware , i also can not accurate to say

what unpredictable behaviour it will be ,  while this is ture , please refer to it .

-- And you said from your project you send to me , i can find the bug , sorry , please point out

where is the bug ?

Hope it hleps

Alice

[davidnemes]

Please see attached file for further explanation of the bug.

[Alice_Yang]

Hello David,

Yes, you are right .

On one hand , you can change it by hand  , then enable the "don't write generated component modules",

on the other hand ,  only use the channels which sharing the same interrupt vector table will

have this error,  so you can use the channels which do not use the same interrupt vector.

BR

Alice

[davidnemes]

The only reason for my reporting the issue is so that the bug can be fixed. Is there any commitment to fix the bug in a future CodeWarrior release?

[Alice_Yang]

Hello David,

So far ,  i don't know when this bug will be fixed ,

and now , for development your project , the  workaround is change it by hand.

BR

Alice