help with chip-to-chip communication

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help with chip-to-chip communication

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voltaic
Contributor I

I am designing a proect for my university where 2 (or more) qy4 series chips using different clocks must communicate with one another, and am not sure how to go about accomplishing this; it seems to me that unless they are using the exact same clock, there is a strong possibility that the data will be corrupted on the way?

 

I'm sure there are ways around this, but don't even know where to begin.  could someone suggest a place to begin reading, or suggest a protocol/method of making this work?

 

Thanks!

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Lundin
Senior Contributor IV
I assume you mean 68HC08 QY4. Those chips have no suitable "peripheral" (ie communications interface) on-chip. You'll have to invent your own communication interface and protocol, which is unnecessary complicated. The best way would have been to get a micro with SPI, SCI or CAN. Nobody develops their own parallel/serial interface just for the sake of it.

The clocks doesn't matter, you will have to use the on-chip timers to get a certain bit rate on your own parallel/serial interface.

If the mcus had support for an external address bus, on which they would all be connected, they'd have to use the same clock. But this practice is typically only used by large processors like 32-bit, as far as I know, the HC(S)08 doesn't even have hardware support for it. Also, for EMI reasons external address busses are frowned upon in automotive/safety-critical applications, which are the kind of applications Freescale micros are mainly designed for.
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voltaic
Contributor I

Thank you for your reply, it was very informative.  

 

so, it sounds like my suspicions are true. 

as far as the requirements of the project, i think that the processor being used is pretty much set in stone.  i'm basically making a dev board for students, which at some point could be connected with other student's boards to have a large scale Conway's Game of Life thing going on, so it's not exactly a huge throughput scenario.  maybe two rounds of 16 bits per iteration, at a rate of maybe 2 iterations per second.  all together yeilding a max throughput of 64 bits per second.

 

that said, if i were to mandate that all interconnected procs use the same clock, i assume that if i were to invent my own protocol i could make this work?

 

my only other concern is that we are talking about having a bunch of boards with their own processors spread out on an area that could easily equal several meters, or tens of meters in the long term.  i assume there would be some things to consider on something of that scale, even when operating in the kilohertz range as far as current delivery of the clock, and inteference.  if i'm correct in this assumption, is there a way to overcome this?

 

Thanks again!

 

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Lundin
Senior Contributor IV
Then I would strongly recommend the HCS08DZ family and a CAN bus, for the following reasons:

- HCS08 has an easy-to-use BDM (3 wire interface) while 68HC08 has the plain horrible, error-prone monitor programming interface.

- The CAN bus can handle hundreds of meters with the bit rate you need, even without a repeater. It is ideal for this application, since only small amount of data need to be sent. There is almost no physical limit of the number of nodes.

- The CAN bus is modern and widely used in the industry.


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voltaic
Contributor I
awesome, thanks very much for the input Peter and Lundin.  This definitely gives me a solid place to start!
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PeterHouse
Contributor I

The first question is do you want peer to peer communication or can you have some type of master unit.

 

The second question is how many pins can you use for communication (not including ground).

 

Some ideas then jump out:

- For Master/slave with one pin you could use a one wire protocol like Dallas Semiconductor.

- For Master/slave with two wires you could use a two wire protocol like Philips IIC.

 

For Peer to Peer it gets more complicated

- with one pin I am sure there is a clever way but it is not coming to me now.

- with two pins you could use a daisy chain like approach where every node receives and passes the data along using regular UART like data with embedded clock.

- with three pins you could use something like IIC or two wire SPI with a third wire for arbitration.

 

Good Luck,

 

Peter House

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