Message Edited by jah on 2006-08-21 11:13 AM
Message Edited by jah on 2006-08-21 11:14 AM
Message Edited by jah on 2006-08-21 11:14 AM
Hi jah,
In the other thread you started on this I thought I already answered this in the last post to it.
If you use 1 pin for the psuedo IRQ it will not affect anything you are doing with the other (including rollover)
There is only one overflow flag/interrupt because there is only one counter!
There is only ONE timer/counter on this device with TWO channels, I believe you are slightly confusing channels with timers. Other devices have multiple timers with multiple channels on each.
Regards David
Hi jah,
If you would enlighten us on what package device you are using it would help very much.
I couldn't believe they would drop the IRQ so I took a look myself.
The 28 pin SOIC package does indeed drop PTD2/IRQ
It has Port D 1,2 and 6 also, so I still do not know which one you are talking about.
1 and 2 share with RESET and BKDG so I doubt they don't exist!
As you and others have said there are other pins that can generate an interrupt that can be used like a IRQ if you like.
Be careful of priority though, IRQ is usually highest so the timer would seem the best choice here in this regard.
Regards David
Hi there,
there *is* IRQ pin --- but needs to be enabled first (see section 5.8.1 of datasheet, register IRQCS).
Item #3 will work too, any timer channel pin can serve as 'irq' pin using its Input Capture feature (see chapter 10.5.2.1).
Hope it helps, Pavel ok2ucx
Hello,
Suggest you look at the data sheet for the MC9S08RG60 device, available from the Freescale web site. This also covers the RD series. I do not quite know what you mean when you refer to an "interruptable I/O pin" for the timer, comparator and SPI peripherals.
Regards,
Mac