What the clock cycle of the HCS08 ?

[HYIU]

Hello,

From the application note "M68HC08 to HCS08 Transition - AN2717", it stated that:

" The M68HC08 CPU clock is equal to the bus clock. The HCS08 CPU clock is twice the speed of the bus

clock. A typical HCS08 has a maximum bus speed of 20 MHz and a maximum CPU speed of 40 MHz.

The documented cycle times for the CPU instructions are still referenced to bus cycles."

Now I from the datasheet of the HCS08 (SH8), there is a term called the BUSCLK:

BUSCLK — The frequency of the bus is always half of ICSOUT.

Then I program the ICS to use the FEI mode, and by default, the FLL should output 1024 x 31.25kHz to 39.0625kHz = 32 MHz to 40 MHz for the ICSOUT,

so by default, the BUSCLK should be 16 to 20 MHz.  This looks fine and match with the previous statement in the application note.  But then, when I write

the following program and measure PORTA bit 0 with a scope, I only got 680 kHz output.  680 x 13 = about 8 MHz.  So this obviously does not match with

what is stated in the application note.  The listed instruction cycle time listed in the assembly instruction table seems to be twice that of the BUSCLK.

	asm ("  BSET 0,0x00000000 ");	// 5 cycles.
	asm ("  BCLR 0,0x00000000 ");	// 5 cycles.
	asm ("  BRA  *-4                    ");	// 3 cycles.

Please tell me how all these "clock cycles" are related, as it seems very confusing.

[iansmusical]

Hi Henry,

I'm not sure if this is relevant to you but there is a register in the ICS that controls the BUSCLK division further to the standard divide by 2. If this register were set to divide it by 2 again then you'd see 8MHz (with an untrimmed reference clock).

Hope this helps.

Regards,

Ian

[HYIU]

Ian,

Thanks a lot for your help.  After I set the ICS BDIV to divide by 1, the CPU instruction clock cycle is now the same as the BUSCLK at 16 MHz.

But I realized that I can only do this after I correctly set the trim value (ICSTRM).  Otherwise the clock cycle might exceed the maximum speed specification.

BR - Henry

[weapon]

Hi Henry,

It's good practice to trim internal clock in the application as it can vary in frequency from part to part by as much as ±25% due to processing variations

in manufacturing if leave it untrimmed. We have an application note to explain that.

http://cache.freescale.com/files/microcontrollers/doc/app_note/AN2496.pdf

Hope it will be helpful.

B.R

XWP