Slave select control with two SPI slaves HCS08AW60

[ColinHall]

Hi,

I have an HCS08AW60 with two slaves on the SPI bus. The slaves are write only so the SPI clock and MOSI are common to both and I have GPIO set up to control the slave selects. The slaves are identical and accept 24-bit commands.

I wrote some simple code to check out the SPI bus hardware and everything is fine; I can write to the devices.
 
My bring-up code does the following:
 
1. Assert SS for the relevant device.
2. Write three bytes with spinlock waits on the transmit buffer empty flag.
3. Leave SS asserted for the device.
 
That is working fine. The problem is when I want to send a second command. There is no receive buffer full flag to tell me that the SPI transaction is completed and the SS can be de-asserted.

It looks like I will have to use a timer to pace the transactions.

I wondered if there is something I am missing? Is there some state information on the transmit shift register that I could read?
 
Any advice is welcome. There will be a spin of the board for other reasons, so I can change the hardware if that would get around this problem.

Regards,
Colin.

[bigmac]

Hello Colin,

To keep the SPI operation simple and straightforward, I would suggest that, for each byte sent, you wait until the SPRF flag becomes set, and then read the SPI1D register to clear the flag.  This will prevent an overrun error, and would apply even though you are not using the MISO data.  This will also ensure that each transaction is completed before you commence a new transaction, to whichever slave device.

Regards,

Mac

Message Edited by bigmac on 2007-06-29 05:35 AM