S08QG8 - Detail BRSET/BRCLR Timing for an I/O port

[YeOldeBDM]

For a qg8 processor, I have this pseudo code:

bSomeBit=1 ;takes 5 bus cyles

bSomeBit=0 ; takes 5 bus cycles

1. Assuming that 'some bit is initially 0', is it guaranteed that the resulting pulse width of the bit of the i/o port is a minimum of 5 cycles. (this would not be the case on a microchip design I am porting from because of their internal decoding internal logic).

2. Anybody got a cool C macro that takes BUS_FREQUENCY as an argument and inserts assy NO-OPS after each bit assignment based on the value of BUS_FREQUENCY? (the numbers aren't important, just the macro template)

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Alban Edit: added part number in subject line.

Message Edited by Alban on 2007-03-22 11:09 PM

[YeOldeBDM]

Thanks for your replies.

[bigmac]

Hello,

Provided the code compiles to use BSET and BCLR instructions, the execution time for each of these instructions is 5 cycles.  This will work for I/O registers in page 0, but these instructions are not available with extended addressing - other methods of bit manipulation would be adopted by the compiler, and the number of cycles would differ.  To ensure that the compiler does use the required instructions, it is probably safer to use inline assembly for this portion of the code.

For more than five cycles between the instructions, you will need additional "padding".  One or more NOP instructions could be inserted, and each NOP will add one cycle - not very efficient if you need a significant amount of padding.  You can get more delay per byte by inserting alternative "benign" assembly instructions, e.g.  TST ,X will provide 3 cycles for a single byte.  Another possibility is to repeat the same BSET or BCLR instruction a number of times (5 cycles for 2 bytes).

If the time taken by the combination of instructions is critical, you will need to disable interrupts during the critical code.

Regards,

Mac

[Alban]

Hi, my half cents worth,

1- Yes on the S08 core, the ASM instructions give a precise predictable behaviour. Pseudo code may be compiled in different ways though. The S08 Reference Manual would be your best friend for number of cycles.

It is not a maximum or minimum, but an exact value of cycles you have in the CPU instruction description.

Alban.