Hi,
I assume that you are talking about the HC08/S08 CPUs.
If the I bit in the CCR is set, no interrupts will be executed (except the RESET or the SWI). This is done with the SEI instruction. To enable the interrupts use the CLI instuction.
When the I bit is cleared, the interrupts in the interupt table is scanned once for every instruction executed.
If one or more than one interrupt is pending, the interrupt with the highest priority, will be executed.
This means that eg if a high priority interrupt, gets a new interrupt before it has finished the current interrupt, the new interrupt will follow immediatly after.
Lower interrupts will then never get executed.
If an interrupt has been set, it can only be reset by the interrupt routine with the clearing of the specific I/O bit.
The HC08/S08 family were designed with limited amount of RAM space. That is the interrupt return table should be of limited size. To do it, it is not recommended to enable interrupts to interrupt other interrupts.
This makes it possible to have low priority interrupts to interrupt higher priority interrupts.
If you still want to do it, use the CLI instruction inside the interrupts.
The answer to your question is, if you enable an interrupt from a peripheral, but you don't enable the interrupt handler, an interrupt can be waiting for an CLI instruction and immediatly be executed after it has been executed.
Regards,
Ake