Pending Interrupts

[pammu]

Hello,

I had one basic question regarding the way pending interrupts are handled.

Assuming while performing RAM test I disable all interrupts. If any interrupt comes during this time, will it be stored as a pending interrupt?

I am seeing a behaviour where a interrupt that is occuring (or supposed to occur) when the interrupts are disabled, is being stored as a pending interrupt.

Is this behavior correct or am I seeing things?

I always thought interrupts are stored as pending, if

The interrupts are enabled

A interrupt occurs when a interrupt is being serviced.

[Ake]

Hi,

I assume that you are talking about the HC08/S08 CPUs.

If the I bit in the CCR is set, no interrupts will be executed (except the RESET or the SWI). This is done with the SEI instruction. To enable the interrupts use the CLI instuction.

When the I bit is cleared, the interrupts in the interupt table is scanned once for every instruction executed.

If one or more than one interrupt is pending, the interrupt with the highest priority, will be executed.

This means that eg if a high priority interrupt, gets a new interrupt before it has finished the current interrupt, the new interrupt will follow immediatly after.

Lower interrupts will then never get executed.

If an interrupt has been set, it can only be reset by the interrupt routine with the clearing of the specific I/O bit.

The HC08/S08 family were designed with limited amount of RAM space. That is the interrupt return table should be of limited size. To do it, it is not recommended to enable interrupts to interrupt other interrupts.

This makes it possible to have low priority interrupts to interrupt higher priority interrupts.

If you still want to do it, use the CLI instruction inside the interrupts.

The answer to your question is, if you enable an interrupt from a peripheral, but you don't enable the interrupt handler, an interrupt can be waiting for an CLI instruction and immediatly be executed after it has been executed.

Regards,

Ake

[pammu]

I agree with the Interrupt execution part. My doubt is a bit different.

Assume I disable interrupts while checking the RAM. When I am performing the RAM test, I am supposed to get a CAN Interrupt (obviously I wont get the interrupt as they are disabled).

Now my questions:

Will this interrupt be stored as a pending interrupt?

When I enable the interrupts after the RAM test, will I get the previously occured (supposed to occur) CAN interrupt ?

[kef]

Yes, CAN interrupt won't disappear just because you had I-bit or CAN interrupt enable bits cleared. Module interrupt flags is that memory that "remembers" about interrupts.

[bigmac]

Hello,

A further brief comment -

The various status flags associated with a peripheral are set quite independently of whether interrupts are enabled, or not, either locally or globally.  This is so that polling operation is possible.  Mostly, each flag must be cleared by means of a specific flag clearing sequence, and will remain set until this process is completed, or reset occurs.

Onlly two instances come to mind, where the flag is automatically cleared upon commencement of the ISR code, i.e. external interrupt, and the keyboard interrupts.

Regards,

Mac