Hi Mac,
Excellent! This is just the info that I needed. So, let me see if i understand you perfectly....
I need to wake from sleep with ~120us of slave select (SS) in order to RX a 1MHz SPI slave CMD. To RX a command a that speed, f_bus must be > 4Mhz. BUSCLK = ICSOUT / 2^n, so if n=0, ICSOUT min is 8MHz.
To meet the above conditions and be low power, I could use an external 32.768k watch crystal, leave it on in STOP and draw ~70uA, upon IRQ (SS), wakeup and enable the FLL to run at say, 16-20MHz. Even though the FLL freqency would not be "aquired" (guarnteed within limits), it would be well above FBUS_min to RX my 1MHz SPI slave message, from this point, I could wait until the FLL aquired to do my timing critical tasks and I would have the message in the SPI data register?
I guess the only real question is how long it takes for the FLL output to be released to DCO out from enable? The DCO's have to have some startup time, right? Please excuse me, I dont really understand the operation of a FLL.
Thanks again for the info
I'm looking at the reference manual figures 11-2 and 1-2, pages 206 and 24 respectively.
Message Edited by ajacks504 on
2008-07-24 09:35 PM