DDR Stress test failing for single channel LPDDR2

[srinivasaporam]

Hi,

We have connected single channel LPDDR2 (32bit) with IMX6D board. When we are running DDR Stress test it is failing to read/write values. the schematic for LPDDR2 is attached. and also script with which we are running stress test is also attached. Can anybody guide us whether schematic is OK or not and why DDR stress test is not succeeding???

Original Attachment has been moved to: LPDDR2.inc.zip

[srinivasaporam]

Hi,

Even if they are not swapped, atleast we should get some wrong values... But DDR stress test is completely failing...

it is giving the following result:

============================================

        DDR Stress Test (2.2.0)

        Build: Sep 29 2015, 22:20:56

        Freescale Semiconductor, Inc.

============================================

============================================

        Chip ID

DIGPROG(0x020c8260) = 0x00630002

CHIP ID = i.MX6 Dual/Quad (0x63)

Internal Revision = TO1.2

============================================

============================================

        Boot Configuration

SRC_SBMR1(0x020d8004) = 0x00003050

SRC_SBMR2(0x020d801c) = 0x29000001

============================================

============================================

        DDR configuration

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is LPDDR2 in 1-channel mode.

Data width: 32, bank num: 8

Row size: 14, col size: 9

Chip select CSD0 is used

Density per chip select: 256MB

============================================

Current Tempareture: 42

============================================

DDR Freq: 528 MHz

Note: Array result[] holds the DRAM test result of each byte. 

      0: test pass.  1: test fail 

      4 bits respresent the result of 1 byte.   

      result 0001:byte 0 fail.

      result 0011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000 result[00]=0x1111

ABS_OFFSET=0x04040404 result[01]=0x1111

ABS_OFFSET=0x08080808 result[02]=0x1111

ABS_OFFSET=0x0C0C0C0C result[03]=0x1111

ABS_OFFSET=0x10101010 result[04]=0x1111

ABS_OFFSET=0x14141414 result[05]=0x1111

ABS_OFFSET=0x18181818 result[06]=0x1111

ABS_OFFSET=0x1C1C1C1C result[07]=0x1111

ABS_OFFSET=0x20202020 result[08]=0x1111

ABS_OFFSET=0x24242424 result[09]=0x1111

ABS_OFFSET=0x28282828 result[0A]=0x1111

ABS_OFFSET=0x2C2C2C2C result[0B]=0x1111

ABS_OFFSET=0x30303030 result[0C]=0x1111

ABS_OFFSET=0x34343434 result[0D]=0x1111

ABS_OFFSET=0x38383838 result[0E]=0x1111

ABS_OFFSET=0x3C3C3C3C result[0F]=0x1111

ABS_OFFSET=0x40404040 result[10]=0x1111

ABS_OFFSET=0x44444444 result[11]=0x1111

ABS_OFFSET=0x48484848 result[12]=0x1111

ABS_OFFSET=0x4C4C4C4C result[13]=0x1111

ABS_OFFSET=0x50505050 result[14]=0x1111

ABS_OFFSET=0x54545454 result[15]=0x1111

ABS_OFFSET=0x58585858 result[16]=0x1111

ABS_OFFSET=0x5C5C5C5C result[17]=0x1111

ABS_OFFSET=0x60606060 result[18]=0x1111

ABS_OFFSET=0x64646464 result[19]=0x1111

ABS_OFFSET=0x68686868 result[1A]=0x1111

ABS_OFFSET=0x6C6C6C6C result[1B]=0x1111

ABS_OFFSET=0x70707070 result[1C]=0x1111

ABS_OFFSET=0x74747474 result[1D]=0x1111

ABS_OFFSET=0x78787878 result[1E]=0x1111

ABS_OFFSET=0x7C7C7C7C result[1F]=0x1111

ERROR FOUND, we can't get suitable value !!!!

dram test fails for all values.

Error: failed during ddr calibration

Can you suggest what could be wrong. Whether Script aid we are entering some wrong values or else we are doing some thing wrong...

whats the way that we can make our LPDDR2 pass the stress test. We are using Micron's MT42L64M32D1TK-18 IT:C

[srinivasaporam]

Hi,

We cannot change schematic because board has been fabricated and assembled. Can we do anything in the software to overcome this issue like swapping the values of registers.

is there any way to make our DRAM (LPDDR2) to work? Please suggest us necessary steps.

[igorpadykov]

unfortunately there no ways to do anything in the software

[igorpadykov]

Hi Srinivasa

one schematic bytes 2,3 swapped [D16-23 and D24-31] on memory side, while

associated with them byte controls DQS2,3,DQM2,3 not swapped.

Also it may be useful to look at

LPDDR2 pin swapping on i.MX6DL, can or not?

Best regards

igor

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