i.MX8MQ with ADV7280A-m

[subhasishghosh]

We are trying to integrate ADV7282A-M with i.MX8MQ using the MIPI CSI2 interface and Linux Kernel.

We are using the open source ADV7282A-M driver: drivers/media/i2c/adv7180.c from Kernel Version 4.14.98 (from NXP BSP: imx-yocto-L4.14.98_2.2.0)

While testing, we are not receiving any frames, however the gstreamer command is not throwing any errors.

It seems that V4L2 QBUF IOCTLS are called, however DQBUF IOCTLS is not called since we are not receiving any frames.

gst-launch-1.0 -v --gst-debug-level=2 v4l2src device=/dev/video1 norm=PAL ! 'video/x-raw, format=(string)UYVY,width=720,height=480,framerate=(fraction)30/1,interlace-mode=(string)mixed' ! videoconvert ! autovideosink

We are observing almost all possible errors on the MIPI controller of i.MX8MQ

 root@imx8mqevk:~# /unit_tests/memtool -32 0x30b6010C 1

E

Reading 0x1 count starting at address 0x30B6010C

0x30B6010C:  0000003F

 [0] – crc error
[1] – one bit ecc error
[2] – two bit ecc error
[3] – ULPS status change
[4] – DPHY ErrSotHS has occurred
[5] – DPHY ErrSotSync_HS has occurred
[6] – DPHY ErrEsc has occurred
[7] – DPHY ErrSyncEsc has occurred
[8] – DPHY ErrControl has occurred

Are there any guidelines on how to debug this. Is it signal integrity or clock issue ?

Following is the DTS config:

        adv7282_mipi2: adv7282_mipi2@21 {

                compatible = "adi,adv7282-m";

                reg = <0x21>;

                status = "okay";

                pinctrl-names = "default";

                pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi_rst>;

                clocks = <&clk IMX8MQ_CLK_CLKO2>;

                clock-names = "csi_mclk";

                assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;

                assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;

                assigned-clock-rates = <20000000>;

                csi_id = <1>;

                pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;

                mclk = <24000000>;

                mclk_source = <0>;

                cvbs = <1>;

                port {

                        adv7282_mipi2_ep: endpoint {

                                remote-endpoint = <&mipi2_sensor_ep>;

                        };

                };

        };

[igorpadykov]

Hi Subhasish

one can check debugging steps on below link

https://community.nxp.com/thread/498568 

Best regards
igor
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[subhasishghosh]

Hi igor,

Thanks a lot for your reply. I have already seen that post. However, I have not reached a point where I can use even one lane. I am currently receiving various ECC, CRC and SOT errors. I have i.MX8MQ EVM and ADV7282A-M EVMs wired together.

For i.MX6, in the app note AN5305, its mentioned the following:

"If the clocks are not equal to or greater than the camera sensor clock, the MIPI_CSI error state register
MIPI_CSI_ERR1 may indicate the “start of transmission error on data lane x” for the MIPI_CSI_ERR1
bits 0 to 3."

To start with, my first question is if we are facing signal integrity or DPHY clock issues. The BSP works for OV5640, hence is it safe to assume that the clock requirements for DPHY should already be in place for 720x480, YUV422p 30fps. This resolution is common for both OV5640 and ADV7282A-M, except that ADV7282 uses BT656 format.