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Advice please: Low-Power/Low-Current applications and Kinetis devices

Question asked by Dave Dicks on Nov 18, 2011
Latest reply on Aug 1, 2013 by Philip Drake

There doesn't seem to be much guidance on using the Kinetis family devices in low-power applications where the core, and/or some peripherals, must be kept running continuously (maybe at reduced core/system frequency). I expect the information is there "somewhere" in all the hundreds of pages of documentation, but it doesn't appear to be "obvious" (to me).

 

Maybe someone in this forum, or someone from Freescale, can enlighten us all on how to achieve optimal low-power/low-current operation with Kinetis devices. Are there any "Application Notes" on low-power operation with Kinetis?

 

Obviously, Kinetis devices can "run" at high speed for "very short periods" and enter "stop" mode "the rest of the time" to to keep average power/current draw very low, but sometimes it is necesasary to keep some clocks/peripherals running continuously which precludes using "stop" modes. "Wait" mode (core/processor stopped but peripherals running) doesn't seem to make a "huge" difference. According to the Chip Errata, VLPR mode (Very Low Power Run) doesn't work in the silicon revision on a lot of TWR eval boards either.

 

The webpage for the K60 on Freescale's website states "run currents of <200uA/MHz" - How is that figure achieved in practice?

 

...In the spec sheet for the K60 (document "K60P100M100SF2") it states: 56mA typical at 100MHz core/system clock in "run mode" (with all peripherals off) = 560uA/MHz, and 1.25mA typical at 2MHz in "VLPR" mode (with all peripherals off) = 625uA/MHz


...Both of those figures are much higher than the "<220uA/MHz" headline figure quoted by Freescale.

 

How can we expect core and/or peripheral power/current draw to vary as the core/system clock is reduced in the various run/wait modes?

 

Does the "wakeup time" (i.e. transition from "stop" to "run" etc) vary according to the clock/MCG settings?

 

Does the MCG have to be reconfigured after a "stop"->"run" transition, or do all the clocks restart with the "before stop" frequencies/setup without any intervention?

 

How long does it take the MCG clock signals (when FLL is used) to stabilise after a "stop"->"run" transition? Is that "stabilisation time" taken care of in the <6uS "wake up times" quoted in the specsheets?

 

Using a 32.768KHz crystal to generate a RTC clock which can then also be used with the FLL to create higher frequency accurate core/system clocks looks attractive... is that a good option for low-power applications?

 

What are the "gotchas" in switching the core, system and/or peripheral clock frequencies "on the fly" ?

 

How does switching clock frequencies and/or using "stop" modes affect MQX? Does MQX include support for the low-power modes of Kinetis?

 

Am I missing something obvious: Can <220uA/MHz in a "run mode" really be achieved with Kinetis family devices in practical situations?

 

There are a lot of clocking (and other) options available to us in the Kinetis chips, and a lot of register settings which can be adjusted in different ways - it would seem that MCG setup and choice of clock generation arrangements are critical for best low-power "run" operation, but it isn't clear from the documentation which options are best.

 

What are Freescale's recommendations for obtaining the low run currents that are suggested by the "headline" <220uA/MHz figure?

 

 

 

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