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SPI Master-Slave communication between two MC9S12DG256's

Question asked by Guest on Mar 2, 2011
Latest reply on Mar 8, 2012 by Jose Ribeiro

Hello,

I am trying to communicate between two MC9S12DG256's using SPI protocol having one as master and the other one as a slave. I wrote the following codes following some postings which were uploaded to this forum, but I couldn't make them work. These postings are

 

https://community.freescale.com/message/24342#24342

https://community.freescale.com/message/25173#25173

 

 

First the connection b/w the master and the slave:

 

// Connections:
// MASTER                     SLAVE
// -------------------------------------
// PS4 (MISO) <------------   PS4(MISO)
// PS5 (MOSI) ------------>   PS5(MOSI)
// PS6 (SCLK) ------------>  PS6(SCLK)
// PS7 (SS)   <-- Vcc   
// PS0 (GPIO) ------------>   PS7(SS)
// GND             -------------   GND

 

 

Then, the code for the master:

 

void main(void) {
  volatile byte data; 
 
  PLL_init();  // set system clock frequency to 24 MHz

  // SPI communication initialization as a master
  SPI0BR  = 0b00000011;    // Baud rate = 24MHz/16 = 1.5MHz 0x53; 
  SPI0CR2 = 0b00000010;  // SPI0CR2_SPISWAI=1 : Stop SPI clocks when in wait mode
  SPI0CR1 = 0b01010110;  // Enable SPI ; Master mode ; CPHA = 1 ;

                                                 // SSOE=1 (SS input with MODF feature)      
  DDRS |= 0x61;   // 0b 0 1 1 0 0 0 0 1 : PS7(SS) and PS4(MISO) are input and PS6(SCK)

                               // and PS5(MOSI) are output, PS0 is output for setting and clearing slave's SS
 
  PTS &= (~0x01);                  // Low slave's SS


  for( ; ; ){   
   
    //PTS &= (~0x01);              // Low slave's SS
               
    // Send a byte to the slave
    while( SPI0SR_SPTEF == 0); // Wait until SPIDR becomes empty.
    SPI0DR = 0x04;                         //  Clear the flag SPI0SR_STEF 

    while( SPI0SR_SPIF == 0 );   // Wait until the end of an SPI transfer.   
    data = SPI0DR;                        // Read or write to clear SPI0SR_SPIF flag       
   
    // Receive a byte from the slave
    while(SPI0SR_SPTEF == 0);  // Wait until the SPI0DR is empty
    SPI0DR = 0x00;                         // Read SPI0DR to clear the SPI0SR_SPTEF flag
    while(SPI0SR_SPIF == 0);      // Wait until a SPI transfer is finished   
    data = SPI0DR;                         // Write the received data to data           
   
    //PTS |= (0x01);               // High slave's SS           
  }
}

 

  

For the slave, I have:

 

void main(void) {
  volatile byte data;
 
  PLL_init();        // set system clock frequency to 24 MHz  
 
  // Initialization of SPI communication as a slave 
  SPI0BR =  0b00000011; // baud rate = 24MHz/16=1.5MHz ; 0x53;
  SPI0CR2 = 0b00000010; // SPI0CR2_SPISWAI=1 : Stop SPI clocks when in wait mode
  SPI0CR1 = 0b01000110; // SPI enable ; slave mode ; CPHA=1 ;

                                                // SSOE=1(SS input with MODF feature) ;
  DDRS &= 0x00;
  DDRS |= 0x10;      // 0b 0 0 0 1 0 0 0 0  : PS7(SS), PS6(SCK), PS5(MOSI) are input

                                  // and PS4(MISO) is an output
 
  for( ; ; ) {                   
    // Receive a byte from the master
    //while(SPI0SR_SPTEF == 0); // wait until SPI0DR becomes empty
    //SPI0DR = 0x00;                        // clear the SPI0SR_SPTEF flag
    while(SPI0SR_SPIF == 0);      // wait until the end of an SPI transfer.
    data = SPI0DR;                         // Reads the byte and clears the flag SP0SR_SPIF.

         
    // Send a byte to the master   
    if( data == 0x04){
      while(SPI0SR_SPTEF == 0); //Wait until SPIDR becomes empty.
      SPI0DR = 0x08;
    }else{
      while(SPI0SR_SPTEF == 0); //Wait until SPIDR becomes empty.
      SPI0DR = 0x80;
    }   
    while(SPI0SR_SPIF == 0);    // wait until the end of an SPI transfer. 
    data = SPI0DR;                       // dummy reading to clear SPI0SR_SPIF flag.   
  }
}

 

Running these codes, it seems like that the execution hangs at some of the while loops waiting for the SPIF flag to be set (although I am not very sure). 

 

Alternatively,  I also tried to run the programs by assigning CPHA=0 for both master and slave, and use the PTS_PTS0 bit to bring the slave's SS line to down and then up (you can see this from the commented instructions in the code for the master), but even this trial didn't give positive results.

 

I'd appreciate if anyone could help me.

 

Thanks,

Jaeyun

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