Stephen Malchi

MPC8548E bring up

Discussion created by Stephen Malchi on Jul 24, 2009
Latest reply on Oct 23, 2009 by Ronald Collins

Hi,

 

We at SDSP designed a new PMC/XMC quad ADC card with a xilinx virtex-5 FPGA and MPC8548E core.

 

http://www.sundancedsp.com/products.php?action=detail&param=89

 

I am trying to bring up the MPC using a USB tap and am getting the foloowing error

 

CCSProtocolPlugin: Failed to reset the target

[Draco/m HIP8: ELF is not in expected HALT mode]

 

Can someone tell me how to debug this error?

 

The config signals are asserted via a CPLD. And these are the values set during HRESET

 

cfg_sys_pll    <= "0101"         when config='1' else "ZZZZ";   
cfg_core_pll    <= "110"          when config='1' else "ZZZ";   
cfg_rom_loc    <= "110"          when config='1' else "ZZZ";   
cfg_host_agt    <= "111"          when config='1' else "ZZZ";   
cfg_io_ports    <= "111"          when config='1' else "ZZZ";
cfg_cpu_boot    <= '1'            when config='1' else 'Z';   
cfg_boot_seq    <= "11"           when config='1' else "ZZ";   
cfg_pci1_clk    <= '1'            when config='1' else 'Z';   
cfg_pci1_speed    <= '1'            when config='1' else 'Z';   
cfg_pci1_impd    <= '1'            when config='1' else 'Z';   
cfg_pci1_arb    <= '1'            when config='1' else 'Z';   
cfg_pci1_mode    <= '0'            when config='1' else 'Z';   
cfg_gp_input    <= (others => '0')when config='1' else (others => 'Z');   
cfg_srds_en    <= '0'          when config='1' else 'Z';

 

Config is active for 100 us and 2 sysclks after the HRESET is deasserted. Then all the signals are tristated. The sysclk is running at 100MHz.

 

Best Regards,

Sdsp.

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