My name is Daniele Fingolo and I am a software developer of SMH Technologies.
I'm trying to program the S9KEAZN64 device in question with a programmer that we developed.
We are able to communicate with the Arm Cortex interface via the SWD protocol.
So we are able to write to the core and device registers but we have a problem that seems to be attributable to the watchdog.
In fact we notice the following behavior:
When we power the microcontroller and bring the reset to a HIGH logic state, we periodically see that the reset goes LOW for a few moments and then returns high. This behavior is repeated by resetting the device. Therefore it would not be possible to continue programming if the device is reset after a certain time interval (about twentythree microseconds).
But we have seen that by putting the core in HALT, this behavior no longer occurs.
So we speculated that it depends on the watchdog.
But with the code that we have developed we cannot disable it, because once the core with the code to disable the watchdog is restarted, the latter is not disabled.
I tried to put the same code both in RAM and Flash. In both the cases the watchdog hasn't been stopped.
Attached you will find the source code .C we used and it doesn't seem to work.
The watchdog refresh is not working either.
Attached are also the acquired images of the reset signal.
Can you help me?
I need a specific procedure to disable the watchdog for all the duration of the programming process.
Thank you in advance.