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Clock idle level on SPI port LPC54628 not correct during DMA?

Question asked by Carsten Groen on Jul 3, 2020
Latest reply on Jul 7, 2020 by Carsten Groen


we have a design with a LPC54628. Flexcomm6 is configured for SPI Master and is basically working fine (using DMA transfers). However, when looking at CPOL/CPHA, there is something not quite right. During "normal" SPI read/write (setup of slave device etc) the clock idles low between transfers as it should, but once I start DMA, the clock line idles high. No matter if CPOL bit is set or not, the idle level of the SCLK signal is always high between DMA transfers. I have verified the contents of the CFG register and this is 0x05 (as expected) which is CPHA=0 and CPOL=0. Regardless of this, the clock line idles high between DMA transfers.

Whats going on ?