i.MX8DualXPLUS Interfacing two memory on FlexSPI:

[bimal]

HI NXP Team,

We are using i.MX8DualXPLUS processor in our custom platform development, where we need to interface two memory on single FlexSPI interface.

- Quad SPI Flash and Octal SPI flash has to be interfaced on single FlexSPI interface.

Below are some query based on upper requirement:

1) In Run time can be change the memory configuration from one to another, means in run time change the memory form QSPI Flash to Octal SPI flash. Is it possible? Does it require to reboot the processor?

2) To interface two diff memory (QPSI and Octal SPI) on single FlexSPI interface. Should i use an high speed bus multiplexer, which connects the concerned memory to processor at a time?

or only have multiplexer for chip select between this two memory. and route the other signals (Clock and data signals) in daisy chain method?

[igorpadykov]

Hi Bimal

1) In Run time can be change the memory configuration from one to another, means in run

>time change the memory form QSPI Flash to Octal SPI flash. Is it possible?

yes

>Does it require to reboot the processor?

no

>2) To interface two diff memory (QPSI and Octal SPI)..

please look at sect.18.2 Flexible SPI Controller (FlexSPI), sect.18.2.4.3 Flash

Connection i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual

Best regards
igor
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[bimal]

Thanks for the details,

In addition to above below are follow-up query:

1)As i can see the connection diagram mentioned of interfacing multiple memory without any multiplexer. But that will create stub in Clock and Data lines. Will it not be an problem in high speed operating of QSPI and OSPI (133MHz)?

2) Gone thorugh the section 18.2.4.3 of reference manual, which states to interface two different CS to diff memory, But in my case both memory has to be bootable. So is the booting possible with both chip select or restricted to one only?

(AS i know is like QSPIA_SS0_B can be used for interfacing booting memory but can i use QSPIA_SS1_B for interfacing booting memory also what about QSPIB_SS0_B interfacing?)

Looking for your valuable feedback.

[igorpadykov]

>1..Will it not be an problem in high speed operating of QSPI and OSPI (133MHz)?.

one can perform ibis modelling for that case

2) only one QSPI is supported for boot, one can look at Chapter 5 System Boot

i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual

Table 5-21. FlexSPI IOMUX Pin Configuration. Also there is "Parallel Mode Enable"

described in Table 5-19. FlexSPI Configuration block.

Best regards
igor

[bimal]

Parallel Mode is for Octal Flash right? Correct me if i am having wrong understanding.

1) Apart form that, Was not able to find the boot configuration changes that has to be done to change the boot from eMMC to QSPI and QSPI Flash to Octal Flash.

Didn't got details to change the boot configuration from QSPI Flash to Octal Flash or viceversa. Can you please provide some example for the same.

[igorpadykov]

for new questions please create new threads.

Best regards
igor