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FlexSPI boot and XIP operation in Parallel flash mode - 100 Pin LQFP Package IMXRT1021

Question asked by Jawahar Arumugam on Apr 11, 2020
Latest reply on Apr 27, 2020 by Victor Jimenez

Hi, I am developing a new hardware based on IMXRT1021, 100 pin LQFP package. I planned to use Serial NOR Flash (Adesto AT25SF128A Flash) connected to  FlexSPI for booting and then XIP  in parallel mode. i.e. I want to use two Flash devices one in FlexSPI_A and FlexSPI_B so that the data width becomes 8 bit.

When I go through the IMXRT1020CEC.pdf document, I find that Flash CS pin assigned to FlexSPI_B at boot time, GPIO_SD_B0_04,  is not available in 100 pin LQFP package. In XIP mode, after the boot process is over, the boot code transfers the control to the application in Flash, hence application code may not be able to configure alternate pin for FlexSPI_B CS signal. 

My conclusion is that with IMXRT1021, 100 pin package, I cannot use FlxSPI boot flash in parellel mode for XIP operation, (unless I run the initial code from RAM (copied into RAM as part of boot process from single flash connected to FlexSPI_A) , then reconfigure the pins for FlexSPI_B and then transfer control to XIP code in parallel flash).

Is my understanding correct?

Thanks

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