This question refers to the I.MX8 nano which is based on ARM Cortex A-53.
I would like to get a better understanding regarding the relation between the core (ARM Cortex A53 64-bit) and the external memory LPDDR4 from performance perspective.
According to i.MX 8M Nano Applications Processor Reference Manual document (Document Number: IMX8MNRM
Rev. 0, 12/2019), the DRAM controller and PHY includes:
• LPDDR4-3200, DDR4-2400, and DDR3L-1600 in Non-POP BGA package
• 16-bit DRAM interface
• 800MHz 64-bit AXI bus
Let's assume that the external memory is an LPDDR4-3200 16-bit wide (transfer rate of 3200 MT/s --> 1.6GHz I/O bus clock). Taking into account that the external memory is DDR it means that the memory can handle 32-bits in one clock. Both AXI Bus and the A53 are 64-bit wide. However the frequency of the AXI bus is half (800MHz) of the frequency of the A53(1.5GHz).
If all of the above is correct, this architecture may lead to latency and performance issues. isn't it?
In addition, according to ARM documentation the The A53 L2 memory system interfaces to the external memory is 128-bits wide. how does it match to the fact the the AXI bus is 64-bits wide?