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i.MX8QXP CSI-PIXEL_CLK_POL behavior

Question asked by Mamoru Kanou on Mar 9, 2020
Latest reply on Mar 23, 2020 by Mamoru Kanou

Hello community,

We are connecting a Parallel camera to the CSI interface of i.MX8QXP and trying to capture video.
We are studying the setup time and hold time of each signal for the image input clock of i.MX8QXP. Please tell me about the input clock and the timing of HSYNC input, VSYNC input and data input.
Q)
Is the equivalent circuit of VSYNC_POL, HSYNC_POL, and PIXEL_CLK_POL of the CSI_CTRL_REG_CLR register considered as shown in the attached figure?

 

BestRegards,

Kanou

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