Dear Sir,
I develop a custom board with the LS1043A CPU.
I have somes questions about the DDR4 memory interface of the LS1043A CPU.
We would like to use 4GB of ddr4 memory for our custom board.
For this I have connected two DDR4 MT40A1G16RC-062E_ITB memory (2GB, 1Gbit*16) from Micron on the LS1043A CPU DDR memory interface.
My questions:
1) Do I use one chip select signal for the two DDR memory (D1_MCS0_B signal) or two chip select signals (D1_MCS0_B for the first and D1_MCS1_B for the second DDR4) ?
Chapter 2.2.1 of the "QorIQ LS1043A Reference Manual" said than you can connect only 1 chip select signal.
2) There is no problem to use two MT40A1G16RC-062E_ITB memory with the LS1043A CPU ?
Thank is you in advance for your reply.
Best regards.
1) One - MCS0
2) It is OK to use two MT40A1G16RC-062E_ITB devices with the LS1043A.
Please refer to the AN5097 - Hardware and Layout Design Considerations for DDR4 SDRAM
Dear Sir,
Thank you very much.
With your quick answer my design is finished :smileyhappy:
Best regards
LS1043ARDB-PD Design Files are available here:
QorIQ® LS1043A Development Board | NXP
The RDB board has two memory banks (i.e. MCS0 and MCS1 are used).