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B4860QDS and IFC nandflash 32Gbit

Question asked by zhang zht on Nov 29, 2019
Latest reply on Dec 2, 2019 by zhang zht

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Dear All,

We are using our own customized B4860 processor board. Now we need to the Increase flash capacity from 512M to 4G, and the new nand flash is “MT29F32G08ABCABH1”.

We have configured uboot:

#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
| CSOR_NAND_PGS_8K /* Page Size = 8K */ \
| CSOR_NAND_SPRZ_CSOR_EXT/* Spare size = 448 */ \
| CSOR_NAND_PB(128)) /*Pages Per Block = 128*/

#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 8192)

#define CONFIG_SYS_CSOR0_EXT 0x000001C0

other macros are same as the default.

Now,it can't boot from nand flash.

1.B4860QDS support nand flash "MT29F32G08ABCABH1"?

2.or are there other ignore modifications in uboot?

thank you!

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M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf3.1 MB

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Yiping Wang

Nov 29, 2019 2:16 AM

Hello zhang zht,

You need to calculate IFC timing according to the datasheet of "MT29F32G08ABCABH1".

For details please refer to IFC Controller Configuration on QorIQ Custom Boards

Thanks,

Yiping

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zhang zht @ Yiping Wang on Dec 2, 2019 6:52 PM

Hello,Yiping:

Thank you for your reply. I have calculated IFC Timing according to your method. And I find most of the settings are the same as the default.Now the macro settings is as follow, the red words are modified:

/* NAND Flash on IFC */
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
| CSOR_NAND_PGS_8K /* Page Size = 8K */ \
| CSOR_NAND_SPRZ_CSOR_EXT/* Spare size = 64 */ \
| CSOR_NAND_PB(128)) /*Pages Per Block = 128*/

#define CONFIG_SYS_NAND_ONFI_DETECTION
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 8192)
#if defined(CONFIG_NAND)
/*zzt add on 20191128*/
#define CONFIG_SYS_CSOR0_EXT 0x000001C0
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3

So, it may not be timing configure problem.

Now,I can erase and write nandflash in uboot environment. But read nandfalsh is error:

NAND read from offset 0 failed -74
0 bytes read: ERROR

Maybe I forgot to modify certain items, such as ECC check. Can you help me, Thank you !

Attachments

Flash_Memory_List_Timings_mod.xls138.0 KB

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2 Replies

Yiping Wang Nov 29, 2019 2:16 AM
Mark Correct
Correct Answer
Hello zhang zht,

You need to calculate IFC timing according to the datasheet of "MT29F32G08ABCABH1".
For details please refer to IFC Controller Configuration on QorIQ Custom Boards

Thanks,
Yiping
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- zhang zht @ Yiping Wang on Dec 2, 2019 6:52 PM
  Mark Correct
  Correct Answer
  Hello,Yiping:
  Thank you for your reply. I have calculated IFC Timing according to your method. And I find most of the settings are the same as the default.Now the macro settings is as follow, the red words are modified:
  
  /* NAND Flash on IFC */
  #define CONFIG_NAND_FSL_IFC
  #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  #define CONFIG_SYS_NAND_BASE 0xff800000
  #ifdef CONFIG_PHYS_64BIT
  #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  #else
  #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  #endif
  #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  | CSPR_MSEL_NAND /* MSEL = NAND */ \
  | CSPR_V)
  #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
  | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
  | CSOR_NAND_SPRZ_CSOR_EXT/* Spare size = 64 */ \
  | CSOR_NAND_PB(128)) /*Pages Per Block = 128*/
  
  #define CONFIG_SYS_NAND_ONFI_DETECTION
  /* ONFI NAND Flash mode0 Timing Params */
  #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  FTIM0_NAND_TWP(0x18) | \
  FTIM0_NAND_TWCHT(0x07) | \
  FTIM0_NAND_TWH(0x0a))
  #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  FTIM1_NAND_TWBE(0x39) | \
  FTIM1_NAND_TRR(0x0e) | \
  FTIM1_NAND_TRP(0x18))
  #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  FTIM2_NAND_TREH(0x0a) | \
  FTIM2_NAND_TWHRE(0x1e))
  #define CONFIG_SYS_NAND_FTIM3 0x0
  #define CONFIG_SYS_NAND_DDR_LAW 11
  #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  #define CONFIG_SYS_MAX_NAND_DEVICE 1
  #define CONFIG_MTD_NAND_VERIFY_WRITE
  #define CONFIG_CMD_NAND
  
  #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 8192)
  #if defined(CONFIG_NAND)
  /*zzt add on 20191128*/
  #define CONFIG_SYS_CSOR0_EXT 0x000001C0
  #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
  #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  So, it may not be timing configure problem.
  Now,I can erase and write nandflash in uboot environment. But read nandfalsh is error:
  NAND read from offset 0 failed -74
  0 bytes read: ERROR
  Maybe I forgot to modify certain items, such as ECC check. Can you help me, Thank you !
  Attachments
  - Flash_Memory_List_Timings_mod.xls138.0 KB
  Like • Show 0 Likes0
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B4860QDS and IFC nandflash 32Gbit

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