I'm looking for efficient way to handle individual GPIO pins from different Cores.
If pin is allocated to some peripheral role it is there.
But after that remains individual pins in Bank 0 and 1 what should be controlled from Core 1 or Core 0.
So the same pin is clearly used only from one Core but due common registers it might be problem
to read state of PIO1_9 state and change ouput value of PIO1_10 from other Core.
From other side all registers are 32 bit wide and it can be atomic operation to read or write one 32 bit register.
If pins grouped to GINT0/1 or PINT it might be not a problem because the controlled via other peripherals blocks.
But what can be problem to handle individual GPIO pins in one Bank from different Cores ?