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LPC55S69 : nIRQ pin allocation

Question asked by Eugene Hiihtaja on Oct 31, 2019
Latest reply on Nov 11, 2019 by Alexis Andalon

Hi !

 on page of UM 207-209 I can read this kind of recommendations:



The bootloader also supports the active notification pin (nIRQ pin) to notify the host
processor it is busy or ready for new commands/data. See below figure for the typical
physical connection between the host and the bootloader device.




To accelerate the SPI transfer between the host and the bootloader, the bootloader
provides an active notification pin known as the nIRQ pin, it can be enabled by the
SetProperty command. Once being enabled, the host needs to wait until it sees a negative
edge on the nIRQ pin before reading any data from the bootloader, and it needs to wait
until the nIRQ pin is high before sending any data to the bootloader.




But it is not clear what exact GPIO pin can be used for those purposes. And Exact format of message for configure it.

Do you have more info about it ?