AnsweredAssumed Answered

Display pixel clock limitation to 74.25 MHz

Question asked by Sebastian Panceac on Sep 25, 2019
Latest reply on Mar 14, 2020 by Nico Coesel



I'm using a board with the IMX8 SoC and 4.14.98 IMX kernel.


I'm trying to add support for a MIPI-DSI display (800x480@60Hz) that needs a pixel clock of ~25MHz.


The problem is that there is a minimum limit for the pixel clock of 74.25MHz, both in the LCDIF and DCSS driver.


In the drivers there is mentioned a TODO about fixing this minimum limit.


Any plans or timeline on fixing this clock limit?


Thank you!