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Display pixel clock limitation to 74.25 MHz

Question asked by Sebastian Panceac on Sep 25, 2019
Latest reply on Oct 14, 2019 by Sebastian Panceac

Hi,

 

I'm using a board with the IMX8 SoC and 4.14.98 IMX kernel.

 

I'm trying to add support for a MIPI-DSI display (800x480@60Hz) that needs a pixel clock of ~25MHz.

 

The problem is that there is a minimum limit for the pixel clock of 74.25MHz, both in the LCDIF and DCSS driver.

 

In the drivers there is mentioned a TODO about fixing this minimum limit.

 

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/mxsfb/mxsfb_drv.c?h=imx_4.14.98_2.1.0#n249
https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/imx/dcss/dcss-dtg.c?h=imx_4.14.98_2.1.0#n371

 

Any plans or timeline on fixing this clock limit?

 

Thank you!

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