Hi NXP team,
For FS85 PMIC, Is it possible to configure the following OTP registers through FS85 driver during init :
1. WD_SELECTION bit of OTP_CFG_ASIL register for challenger mode
2. FLT_RECOVERY_EN bit of OTP_CFG_I2C register for disabling the fault recovery strategy
3. Autoretry_infinite and Autoretry_en bits of OTP_CFG_SM_2 register
If not how these OTP registers shall be configured?
Regarding point3 : Will the FS85 move to DEEP_FS when fault error counter reaches maximum?
(According to FS85 data sheet, Exit of DEEP-FS mode is only possible by WAKE1 = 0 or after 4 s if the autoretry feature
is activated by OTP_Autorety_en bit. The number of autroretry can be limited to 15 or infinite depending on OTP_Autoretry_infinite bit.)
So after recovering from DEEP_FS when wake1 = 1, the main state machine will start transition to normal mode. I would like to know the state to which FS_state machine will transit or in other words how will FS_state machine behave?
(Note :The FS85 is connected to MCU for watchdog purpose)