I'm planning to use LPC 55S6X MCU's in one of my product and wanted to add USB3.0 connectivity for more data rate.
Now, if we employ FTDI 601Q/ Cypress EZ USB FX3 chips (USB 3.0 to FIFO Bridge IC), as a middle IC bw Host and main MCU (LPC 55X), they atleast need 16/32 bit wide FIFO bus on the MCU end to interface with.
In LPC 55S6X Data sheet, FIFO mentioning is in the following:
* 2 exclusive HIgh speed SPI fifo with 8 entries
* Every Flexicom (0-7) has a FIFO for implementing USART, SPI, I2S.
* Two independent result FIFOs for ADC, each contains 16 entries.
I want to know, if I can use any of the above FIFO's (especially SPI/ADC FIFO's) without any difficulty to interface with my USB 3.0 to FIFO Bridge IC
Am I missing any technical difficulties in implementing this ?
Thanks in advance.