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SPI Slave Configuration for the LPC1549 ( LPC15xx )

Question asked by Victor Maslov on Jun 12, 2019
Latest reply on Jun 17, 2019 by Alice_Yang

I'm currently evaluating the SPI slave functionality of the LPC1549.

 

I'm wondering if there is any examples not using the ROM API, I'd like to be able to tweak the ISR to my liking and have more control on what's being transmitted.

 

Is there a data rate limit?

 

It seems like a feature that even the user guide lacks proper explanation and configuration of this state for the peripheral.

 

Currently I have the following configurations using LPCOPEN  :

   

for this example I'm using SPI0

 

 - Set GPIO direction for general SPI and a CS 

 

- Set the SWM settings corresponding to the proper PINASSIGN banks for SWM_SPI0_MOSI_IO, SWM_SPI0_SCK_IO, and SWM_SPI0_MISO_IO

 

- I then set the CS the same as if I were to be in Master mode ( Except CS is set to input ).

 

After initialization , the following configurations are set in the SPI0 peripheral register : 

Once I send the following capture, The SSA ( Slave Select Assert ) and SSD ( Deassert ) are found to be set, but I would expect the RXRDY to be set as well.

 

 

Let me know if you guys require additional information, I'd love to chat about this!

 

 

Victor

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