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Common Ethernet RMII designfor I.MX6UL, Dual and QuadPlus

Question asked by Christophe Niclaes on May 13, 2019
Latest reply on May 16, 2019 by Christophe Niclaes

I'm designing a CPU module that must fit on a custom motherboard. This motherbqrd can be used with several types of CPU modules with either IMX6UL, IMX6Dual/Quad or IMX6DualPlus/QuadPlus.

 

My concern is about having a common design for all CPUs regarding the reference clock of the Ethernet port.

 

1. On my IMX6UL CPU Module, I use a design very close to the EVK. The ENET1 interface is configured as RMII and ENET1_TX_CLK is an output going to the PHY licated on my motherboard.

2. How can I do that for IMX6Dual/Quad ? It seams that ENET_TX_CLK and ENET_RX_CLK are always inputs and are not used in RMII mode. Another signal, ENET_REF_CLK, is also an input. There is an internal REFCLK generator in the clocking module but how to use it? I would lije this generator to provide the clock to the IMX6's MAC and to my PHY on the motherboard.

3. I want my IMX6Dual/Quad module to be able to host an IMXDualPlus/QuadPlus on the same PCB. It seams that there is a difference with the Plus version: ENET_TXCLK_SEL bit in IOMUXC_GPR5. What's the impact. How to have a design tha fits all CPUs?

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