iMX6SX dual MDIO bus

[abelussi]

Our board use two MDIO bus (ENET_MDIO1-pinE7 + ENET_MDC1-pinF9, ENET_MDIO2-pinC7 + ENET_MDC2-pinE6)  to connect two physical ethernet (KSZ9031-Micrel) with a physical address "0x3" and "0x7", and we set the device tree as:

pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 /* GPIO2_IO03 - E7 */
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 /* GPIO2_IO02 - F9 */
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 /* GPIO5_IO11 - E11 */
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 /* GPIO5_IO06 - C12 */
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 /* GPIO5_IO07 - D12 */
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 /* GPIO5_IO08 - E12 */
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 /* GPIO5_IO09 - C11 */
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 /* GPIO5_IO10 - C10 */
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 /* GPIO5_IO05 - D10 */
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 /* GPIO5_IO00 - D8 */
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 /* GPIO5_IO01 - E9 */
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 /* GPIO5_IO02 - C8 */
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 /* GPIO5_IO03 - E8 */
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 /* GPIO5_IO04 - E10 */
MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0xb0b1 /* GPIO1_IO03 - D20 - */
>;
};

pinctrl_enet2: enet2grp {
fsl,pins = <
MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0b1 /* GPIO2_IO01 - C7 */
MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0b1 /* GPIO2_IO00 - E6 */
MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 /* GPIO5_IO23 - A11 */
MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 /* GPIO5_IO18 - A12 */
MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 /* GPIO5_IO19 - B12 */
MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 /* GPIO5_IO20 - A13 */
MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 /* GPIO5_IO21 - B13 */
MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 /* GPIO5_IO22 - B11 */
MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 /* GPIO5_IO17 - A10 */
MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 /* GPIO5_IO12 - A9 */
MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 /* GPIO5_IO13 - B9 */
MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 /* GPIO5_IO14 - A8 */
MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 /* GPIO5_IO15 - B8 */
MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 /* GPIO5_IO16 - B10 */
>;
};

&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-supply = <&reg_enet_3v3>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
status = "okay";

mdio {
#address-cells = <1>;
#size-cells = <0>;

ethphy1: ethernet-phy@3 {
device_type = "ethernet-phy";
reg = <3>;
};
};
};

&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-supply = <&reg_enet_3v3>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy2>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;

ethphy2: ethernet-phy@7 {
device_type = "ethernet-phy";
reg = <7>;
};
};
};

Our problem is that we see only the bus MDIO1 and the FEC0 works fine but the FEC 1 no.

In U-BOOT when we make a command "mdio list" the result is:

=> mdio list
FEC0:
3 - Micrel ksz9031 <--> ethernet@02188000
FEC1:
3 - Micrel ksz9031 <--> ethernet@021b4000

We expect on FEC1 the adddress 0x7, we don't see any signal on MDIO2 pins, have someone any suggestion ??

Thanks in advanced

[jamesbone]

Hello Antonio,

Based on your information Uboot it is able to detect both of the FEC interfaces, this means that you are having a conflict in your Device Tree file, it seems another PIN or PAD it is conflicting with the FEC1 and this way the Kernel it is avoiding to create the second interface.

Have a great day,
TIC

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[abelussi]

i check all pin setting in the device tree and I don't find any conflict.

On the pin ENET1_MDC i found a clock of 2.35 Mhz, on the pin ENET2_MDC (ENET1_COL) I found nothing (zero).

In the u-boot by gpio procedure I can set and clear the pin (1 -> 0 , 0-> 1).

Thanks

[jamesbone]

Hello Antonio,

Are you able to ping both instances FEC0 and FEC1 in Uboot using Ping or any other command just to see, if the problem maybe in the Kernel Config, that it is only accepting one instance, because by default in our BSP, we always use only one. do you think you can share the part of the schematics to see which pads are you using, and follow what else could be the conflict.

Have a great day,
TIC

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Note:
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- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

[abelussi]

I connect the Lauterbach emulator and set the register at low level for enable the ENET_MDIO2 with the same result, no frequency is present on ENET_MDC2. Instead  if I set the register by emulator for enable/disable ENET1_MDC , I found a clock of 2.35 Mhz or not.

At the end I connect by resistor R1167 and R1166 the two FEC 1/2 on the same MDIO1 and all works fine.I can ping the two different ETH address.

Thanks