MPC5777M uart problem on S32DS

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MPC5777M uart problem on S32DS

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1,215 Views
bwp530
Contributor IV

MPC5777M uart can't send or recv any data, when I thransplant Example MPC5777M LINFlex UART Echo SW polling GHS614 to S32DS. It always block at 'while (1 != LINFlexD_2.UARTSR.B.DTFTFF) {}; ' or 'while (1 != LINFlexD_2.UARTSR.B.DRFRFE) {}'  when debuging on matherboard. Can someone help me? martinkovar


void SysClk_Init(void)
{
MC_CGM.AC3_SC.B.SELCTL = 0x01; //connect XOSC to the PLL0 input
MC_CGM.AC4_SC.B.SELCTL = 0x01; //connect XOSC to the PLL1 input

// Set PLL0 to 300 MHz with 40MHz XOSC reference
PLLDIG.PLL0DV.R = 0x4002100F; // PREDIV = 1, MFD = 15, RFDPHI = 2, RFDPHI1 = 8

MC_ME.RUN_MC[0].R = 0x00130070; // RUN0 cfg: IRCON,OSC0ON,PLL0ON,syclk=IRC

// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode

// Set PLL1 to 600 MHz with 40MHz XOSC reference
PLLDIG.PLL1DV.R = 0x0001001E; // MFD = 30, RFDPHI = 1

MC_ME.RUN_PC[0].R = 0x000000FE; // enable peripherals run in all modes
MC_ME.RUN_MC[0].R = 0x001300F4; // RUN0 cfg: IRCON, OSC0ON, PLL1ON, syclk=PLL1

MC_CGM.SC_DIV_RC.R = 0x00000001; //! System clock divider ratios will change with next update. Not required for Cut 1.
MC_CGM.DIV_UPD_TYPE.R = 0x80000000; //! System clock divider ratios updated on writing MC_CGM.DIV_UPD_TRIG. Not required for Cut 1.

MC_CGM.SC_DC2.R = 0x800B0000; // PBRIDGEA/PBRIDGEB_CLK at syst clk div by 12 ... (50 MHz)
MC_CGM.SC_DC1.R = 0x80050000; // SXBAR_CLK at syst clk div by 6 ... (100 MHz)
MC_CGM.SC_DC0.R = 0x80020000; // FXBAR_CLK, BD_CLK, IOP_CLK at syst clk div by 3 ... (200 MHz)
MC_CGM.SC_DC3.R = 0x80010000; // COMP/CHKR_CLK at syst clk div by 2 ... (300 MHz)
MC_CGM.SC_DC4.R = 0x800A0000; // CLKOUT at syst clk div by 11 ... (54.55 MHz)

MC_CGM.DIV_UPD_TRIG.R = 0xfeedface; //! System clock divider ratio updates triggered. Not required for Cut 1.
while (MC_CGM.DIV_UPD_STAT.B.SYS_UPD_STAT == 1) //! Wait for System Clock Divider Update Status == 0. Not required for Cut 1.
{
asm("nop");
}

// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode

MC_CGM.AC0_SC.R = 0x02000000; // Select PLL0 for auxiliary clock 0
MC_CGM.AC0_DC0.R = 0x80050000; // PER_CLK : Enable aux clk 0 div by 6 ?(50 MHz)
MC_CGM.AC0_DC4.R = 0x80020000; // DSPI_CLK1, LIN_CLK : Enable aux clk 0 div by 3 ?(100 MHz)

}

void SUIL2_Init(void)
{
SIUL2.MSCR_IO[4].R = 0x12380000; // toggled in Core 2 while loop
SIUL2.MSCR_IO[0].R = 0x12380000; // toggled in Core 2 PIT ISR

/* Configure pad PD14 for AF1 func: LIN2TX */
SIUL2.MSCR_IO[62].B.SSS = 2; /* Pad PD14: Source signal is LIN0_TXD */
SIUL2.MSCR_IO[62].B.ODC = 2; /* Pad PD14: push-pull Output */
SIUL2.MSCR_IO[62].B.OERC = 3; /* Pad PD14: Maximum slew rate */
/* Configure pad PD15 for LIN0RX */
SIUL2.MSCR_IO[63].B.IBE = 1; /* Pad PD15: Enable pad for input - LIN0_RXD */
SIUL2.MSCR_IO[850].B.SSS = 1; /* LIN0_RXD: connected to pad PD15 */
//SIUL2.MSCR_MUX[338].B.SSS = 1; /* LIN0_RXD: connected to pad PD14 */

}


void LINFlexD_2_Init (void)
{
/* enter INIT mode */
LINFlexD_2.LINCR1.R = 0x0081; /* SLEEP=0, INIT=1 */

/* wait for the INIT mode */
while (0x1000 != (LINFlexD_2.LINSR.R & 0xF000)) {}

/* configure for UART mode */
LINFlexD_2.UARTCR.R = 0x0001; /* set the UART bit first to be able to write the other bits */

LINFlexD_2.UARTCR.R = 0x0033 | TXFIFO << 8 | RXFIFO << 9; /* 8bit data, no parity, Tx and Rx enabled, UART mode */
/* Transmit buffer size = 1 (TDFL = 0 */
/* Receive buffer size = 1 (RDFL = 0) */

/* configure baudrate 19200 */
/* assuming 100 MHz baud clock (LIN_clk below)*/
/* LFDIV = LIN_clk / (16 * desired baudrate)
LINIBRR = integer part of LFDIV
LINFBRR = 16 * fractional part of LFDIV (after decimal point)

for instance:
LFDIV = 100e6/(16*19200) = 325.52083
LINIBRR = 325
LINFBRR = 16*0.52083 = 8
*/

LINFlexD_2.LINFBRR.R = 8;
LINFlexD_2.LINIBRR.R = 325;


/* enter NORMAL mode */
LINFlexD_2.LINCR1.R = 0x0080; /* INIT=0 */
}


void TransmitCharacter(uint8_t ch)
{
// address of LINFLEX_0.BDRL.B.DATA0
unsigned char *pTX = (unsigned char *)&LINFlexD_2.BDRL.R + 3;

#if TXFIFO /* TXFIFO selected */

while (1 == LINFlexD_2.UARTSR.B.DTFTFF) {}; // wait if TXFIFO is full
/* write character to transmit buffer
byte access have to be used in TXFIFO mode
compiler can use word instructions for byte access thus byte pointer is used instead */

//LINFlexD_2.BDRL.B.DATA0 = ch;
*pTX = ch; /* write character to transmit buffer */

#else /* TX buffer mode selected */

*pTX = ch; /* write character to transmit buffer */
while (1 != LINFlexD_2.UARTSR.B.DTFTFF) {}; /* Wait for data transmission completed flag */
LINFlexD_2.UARTSR.R = 0x0002; /* clear the DTF flag and not the other flags */

#endif
}


void ReadCharacter (void)
{

#if RXFIFO /* RXFIFO selected */

while (1 == LINFlexD_2.UARTSR.B.DRFRFE) {} /* Wait if RXFIFO is empty */

rx_data = (uint8_t)LINFlexD_2.BDRM.B.DATA4; /* get the data */

#else /* RX buffer mode selected */

while (1 != LINFlexD_2.UARTSR.B.DRFRFE) {} /* Wait for data reception completed flag */

while (1 != LINFlexD_2.UARTSR.B.RMB) {} /* Wait for Release Message Buffer */

rx_data = (uint8_t)LINFlexD_2.BDRM.B.DATA4; /* get the data */

/* clear the DRF and RMB flags by writing 1 to them */
LINFlexD_2.UARTSR.R = 0x0204;

#endif

}

1 Solution
891 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

your ME_PCTL for SIUL2 is not active. In other words there is no clock for SIUL2 module.

Configure ME correctly as latest cut of device is disabling SIUL in BAF. In you application you have to enable MC_ME_PCTL15 for target mode and do mode translation. Then it will work. Otherwise the pins wont be active.

So use 

MC_ME.PCTL15.R = 0;

before doing final mode transition in SysClk_Init().

Also use register access to config  pins, i.e.

/* Configure pad PD14 for AF1 func: LIN2TX */
SIUL2.MSCR_IO[62].R = 0x32000002;

/* Configure pad PD15 for LIN0RX */
SIUL2.MSCR_IO[63].R = 0x0080000; /* Pad PD15: Enable pad for input - LIN2_RXD */
SIUL2.MSCR_IO[850].R = 1; /* LIN2_RXD: connected to pad PD15 */

BR, Petr

View solution in original post

3 Replies
892 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

your ME_PCTL for SIUL2 is not active. In other words there is no clock for SIUL2 module.

Configure ME correctly as latest cut of device is disabling SIUL in BAF. In you application you have to enable MC_ME_PCTL15 for target mode and do mode translation. Then it will work. Otherwise the pins wont be active.

So use 

MC_ME.PCTL15.R = 0;

before doing final mode transition in SysClk_Init().

Also use register access to config  pins, i.e.

/* Configure pad PD14 for AF1 func: LIN2TX */
SIUL2.MSCR_IO[62].R = 0x32000002;

/* Configure pad PD15 for LIN0RX */
SIUL2.MSCR_IO[63].R = 0x0080000; /* Pad PD15: Enable pad for input - LIN2_RXD */
SIUL2.MSCR_IO[850].R = 1; /* LIN2_RXD: connected to pad PD15 */

BR, Petr

891 Views
bwp530
Contributor IV

so I checkExample MPC5777M LINFlex UART Echo SW polling GHS614 again, the same problem in it.

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891 Views
bwp530
Contributor IV

Thank you very much, it works. And must use register access. my way in code can't work.

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