AnsweredAssumed Answered

S32K ADC CONFIG

Question asked by lei liu on Feb 16, 2019
Latest reply on Feb 19, 2019 by Daniel Martynek

I configured the ADC program, the voltage value and the result of the routine in S32DS are different by 0.9V. Why is this? Is it because I am using software triggering, is the routine using hardware triggering?

ADC_MemMapPtr ADCx[2] = {ADC0, ADC1}; //定义两个指针数组保存 ADCx 的地址
void adc_DMA_init(TYP_ADCn adcn, TYP_ADC_Ch ch)
{

adc_init(adcn, ch) ;//初始化ADC时钟
adc_stop(adcn);

ADCx[adcn]->SC2 = ADTRG_HW //硬件触发
| ACFE_DISABLED
|ACFGT_LESS//| ACFGT_GREATER
| ACREN_DISABLED
| DMAEN_DISABLED
| ADC_SC2_REFSEL(REFSEL_EXT);

ADCx[adcn]->SC3 = CAL_OFF
|ADCO_SINGLE//| ADCO_CONTINUOUS
| AVGE_DISABLED
| ADC_SC3_AVGS(AVGS_4);
ADCx[adcn]->SC1[0] = AIEN_OFF | DIFF_SINGLE |
ADC_SC1_ADCH( ch );
}
void adc_init(TYP_ADCn adcn, TYP_ADC_Ch ch)
{

switch(adcn)
{
case SADC0: /* ADC0 */
PCC->PCCn[PCC_ADC0_INDEX] &=~ PCC_PCCn_CGC_MASK;
PCC->PCCn[PCC_ADC0_INDEX] = PCC_PCCn_CGC_MASK | PCC_PCCn_PCS(1); 

switch(ch)
{
case AD0: //ADC0_SE0-- PTA0
PORTA->PCR[0] |= PORT_PCR_MUX(0);
break;
case AD1: //ADC0_SE1-- PTA1
PORTA->PCR[1] |= PORT_PCR_MUX(0);
break;
case AD2: //ADC0_SE2-- PTA6
PORTA->PCR[6] |= PORT_PCR_MUX(0);
break;
case AD3: //ADC0_SE3-- PTA7
PORTA->PCR[7] |= PORT_PCR_MUX(0);
break;
case AD4: //ADC0_SE4-- PTB0
PORTB->PCR[0] |= PORT_PCR_MUX(0);
break;
case AD5: //ADC0_SE5 -- PTB1
PORTB->PCR[1] |= PORT_PCR_MUX(0);
break;
case AD6: //ADC0_SE6 -- PTB2
PORTB->PCR[2] |= PORT_PCR_MUX(0);
break;
case AD7: //ADC0_SE7 -- PTB3
PORTB->PCR[3] |= PORT_PCR_MUX(0);
break;
case AD8: //ADC0_SE8 -- PTC0
PORTC->PCR[0] |= PORT_PCR_MUX(0);
break;
case AD9: //ADC0_SE9 -- PTC1
PORTC->PCR[1] |= PORT_PCR_MUX(0);
break;
case AD10: //ADC0_SE10 -- PTC2
PORTC->PCR[2] |= PORT_PCR_MUX(0);
break;
case AD11: //ADC0_SE11 -- PTC3
PORTC->PCR[3] |= PORT_PCR_MUX(0);
break;
case AD12: //ADC0_SE12 -- PTC14
PORTC->PCR[14] |= PORT_PCR_MUX(0);
break;
case AD13: //ADC0_SE13 -- PTC15
PORTC->PCR[15] |= PORT_PCR_MUX(0);
break;
case AD14: //ADC0_SE14 -- PTC16
PORTC->PCR[16] |= PORT_PCR_MUX(0);
break;
case AD15: //ADC0_SE15 -- PTC17
PORTC->PCR[17] |= PORT_PCR_MUX(0);
break;

default:
break;
}
break;

case SADC1: /* ADC1 */
PCC->PCCn[PCC_ADC1_INDEX] &=~ PCC_PCCn_CGC_MASK;
PCC->PCCn[PCC_ADC1_INDEX] = PCC_PCCn_CGC_MASK | PCC_PCCn_PCS(1); 
switch(ch)
{
case AD0: //ADC1_SE0-- PTA2
PORTA->PCR[2] |= PORT_PCR_MUX(0);
break;
case AD1: //ADC1_SE1-- PTA3
PORTA->PCR[3] |= PORT_PCR_MUX(0);
break;
case AD2: //ADC1_SE2-- PTD2
PORTD->PCR[2] |= PORT_PCR_MUX(0);
break;
case AD3: //ADC1_SE3-- PTD3
PORTD->PCR[3] |= PORT_PCR_MUX(0);
break;
case AD4: //ADC1_SE4 -- PTC6
PORTC->PCR[6] |= PORT_PCR_MUX(0);
break;
case AD5: //ADC1_SE5 -- PTC7
PORTC->PCR[7] |= PORT_PCR_MUX(0);
break;
case AD6: //ADC1_SE6 -- PTD4
PORTD->PCR[4] |= PORT_PCR_MUX(0);
break;
case AD7: //ADC1_SE7 -- PTB12
PORTB->PCR[12] |= PORT_PCR_MUX(0);
break;
case AD8: //ADC1_SE8 -- PTB13
PORTB->PCR[13] |= PORT_PCR_MUX(0);
break;
case AD9: //ADC1_SE9 -- PTB14
PORTB->PCR[14] |= PORT_PCR_MUX(0);
break;
case AD10: //ADC1_SE10 -- PTE2
PORTE->PCR[2] |= PORT_PCR_MUX(0);
break;
case AD11: //ADC1_SE11 -- PTE6
PORTE->PCR[6] |= PORT_PCR_MUX(0);
break;
case AD12: //ADC1_SE12 -- PTA15
PORTA->PCR[15] |= PORT_PCR_MUX(0);
break;
case AD13: //ADC1_SE13 -- PTA16
PORTA->PCR[16] |= PORT_PCR_MUX(0);
break;
case AD14: //ADC1_SE14 -- PTB15
PORTB->PCR[15] |= PORT_PCR_MUX(0);
break;
case AD15: //ADC1_SE15 -- PTB16
PORTB->PCR[16] |= PORT_PCR_MUX(0);
break;

default:
break;
}
break;
default:
break;
}
}
uint16_t ad_once(TYP_ADCn adcn, TYP_ADC_Ch ch, TYP_ADC_nbit bit)
{
uint16_t result = 0;


adc_start(adcn, ch, bit); //启动ADC转换
while (( ADCx[adcn]->SC1[0] & ADC_SC1_COCO_MASK ) != ADC_SC1_COCO_MASK);
result = ADCx[adcn]->R[0];
ADCx[adcn]->SC1[0] &= ~ADC_SC1_COCO_MASK;
return result;
}
uint16_t ad_ave(TYP_ADCn adcn, TYP_ADC_Ch ch, TYP_ADC_nbit bit, uint8_t N)
{
uint32_t tmp = 0;
uint8_t i;

for(i = 0; i < N; i++)
tmp += ad_once(adcn, ch, bit);
tmp = tmp / N;
return (uint16_t)tmp;
}
void adc_start(TYP_ADCn adcn, TYP_ADC_Ch ch, TYP_ADC_nbit bit)
{

//ADCx[adcn]->CFG1 = 0x000000004;
/* ADICLK=0: Input clk=ALTCLK1=SOSCDIV2 */
/* ADIV=0: Prescaler=1 */
/* MODE=1: 12-bit conversion */
ADCx[adcn]->CFG1 = ADLPC_NORMAL
| ADC_CFG1_ADIV(ADIV_1)//| ADC_CFG1_ADIV(ADIV_4)
| ADC_CFG1_MODE(bit)
| ADC_CFG1_ADICLK(ADICLK_BUS);
ADCx[adcn]->CFG2 = ADC_CFG2_SMPLTS(150);
// ADC_SC2_REG (ADCx[adcn]) =
// | ADACKEN_DISABLED
// | ADHSC_HISPEED
// | ADC_CFG2_ADLSTS(ADLSTS_20) ;
ADCx[adcn]->SC1[0] = DIFF_SINGLE | ADC_SC1_ADCH( ch );
}

Register result as so:

Outcomes