As shown in the schematic diagram attached, playback and capture are on two chips respectively. both of them work in the master mode, imx6q works in the slave mode, playback and capture can work normally, but sometimes there is sudden noise during playback. Looking at TXFS and TXD waveform through an oscilloscope, it is found that there is suddenly no data in the left or right channel when noise is produced, refer to the attachments tek1.png and tek2.png. The waveform without noise is shown in tek0.png.
If RXC/RXFS/RXD is disconnected, the playback will work perfectly, no noise generated, and tek1.png and tek2.png waveforms not generated.
The configuration I have made is as follows. Is there anything missing? If anyone can provide some guidance, it will be appreciated.
The BSP version 4.9.17, which is for android 8.0.0_1.0.0 of imx6, and the chip is imx6q.
/* in the dts, active fsl,ssi-asynchronous */
sound {
compatible = "fsl,imx-dummy-audio";
model = "dummy-audio";
cpu-dai = <&ssi2>;
audio-codec = <&codec>;
asrc-controller = <&asrc>;
audio-routing =
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"CPU-Playback", "ASRC-Playback",
"Playback", "CPU-Playback",
"ASRC-Capture", "CPU-Capture",
"CPU-Capture", "Capture";
mux-int-port = <2>;
mux-ext-port = <4>;
codec-master;
gpr = <&gpr>;
};
&ssi2 {
assigned-clocks = <&clks IMX6QDL_CLK_PLL4>,
<&clks IMX6QDL_PLL4_BYPASS>,
<&clks IMX6QDL_CLK_SSI2_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>,
<&clks IMX6QDL_CLK_PLL4>,
<&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <1179648000>, <0>, <0>;
fsl,ssi-asynchronous;
status = "okay";
};
/* in the audmux, TXC/TXFS/RXC/RXFS get from external port */
ret = imx_audmux_v2_configure_port(int_port,
IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
IMX_AUDMUX_V2_PTCR_RFSEL(ext_port | 0x8) |
IMX_AUDMUX_V2_PTCR_RCSEL(ext_port | 0x8) |
IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TCLKDIR |
IMX_AUDMUX_V2_PTCR_RFSDIR |
IMX_AUDMUX_V2_PTCR_RCLKDIR,
IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
if (ret) {
dev_err(&pdev->dev, "audmux internal port setup failed\n");
return ret;
}
imx_audmux_v2_configure_port(ext_port,
0,
IMX_AUDMUX_V2_PDCR_RXDSEL(int_port));
if (ret) {
dev_err(&pdev->dev, "audmux external port setup failed\n");
return ret;
}
/* in the codec dai, set symmetric_rates = 0*/
static struct snd_soc_dai_driver imx_dummy_codec_dai = {
.name = "imx-dummy-codec-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = imx_dummy_codec_RATES,
.formats = imx_dummy_codec_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = imx_dummy_codec_RATES,
.formats = imx_dummy_codec_FORMATS,},
.ops = &imx_dummy_codec_dai_ops,
.symmetric_rates = 0,
};
Solved! Go to Solution.
This issue has been solved. It's a hardware issue. The reason is that RXC/RXFS/RXD interferes with TXFS signal, which makes SSI unable to recognize TXFS signal correctly.
This issue has been solved. It's a hardware issue. The reason is that RXC/RXFS/RXD interferes with TXFS signal, which makes SSI unable to recognize TXFS signal correctly.
Hi lu
if this is just one board that may be soldering issue. In general one can try
with nxp linux bsps not using model = "dummy-audio", for example with
sound {
compatible = "fsl,imx6q-sabresd-wm8962",
"fsl,imx-audio-wm8962";
model = "wm8962-audio";..
https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm/boot/dts/imx6qdl-sabresd.dtsi?h=i...imx6qdl-sabresd.dtsi\dts\boot\arm\arch - linux-imx - i.MX Linux kernel
Best regards
igor
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Hi, Igor
Thanks for your comment, the dummy-audio is a driver written by my own, it works fine when SSI works in synchronous mode, so may I ask you a question, to the wm8962 audio driver and the ssi/audmux driver, what's the difference when SSI works in synchronous mode and the asynchronous mode?
Hi lu
in synchronous mode, the transmit and receive sections of SSI share a common
clock port (STCK) and frame sync port (STFS).
In asynchronous mode, the transmitter and receiver each has its own clock and frame
synchronization signals.
Best regards
igor
Hi igor
Would you mind pointing out what I am missing according to the modifications I listed before. thanks a lot.
Best regards.
Lu Winbo