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Are MIPI CSI2 "line start" & "line end" Mandatory ?

Question asked by Stephane Tavenard on Dec 7, 2018
Latest reply on Jul 24, 2019 by Zheng Li



We are using iMX6Q and DS90UB954 Ti Deserialiser for capturing video from 2 cameras.

The DS90UB954 is connected to MIPI-CSI2 interface of iMX6Q, using 2 lanes.

The status (PHY_STATE) register show that clock is present (0x00000300), but register MIPI_CSI_ERR1 vlaue is often  0x01001000 (CRC errors)

MIPI_CSI2 signals haved been checked with MPI-CSI2 analyzer (frames ok and no CRC error found)


However, DS90UB954 don't generate short packet frames "line start" and "line end", only short packets "frame start" a "frame end" are present. Do you know if this short packets "line start" and "line end"  are mandatory for IMX6Q MIPI-CSI2 interface ?