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IMX8MQ   How to enable 50M HZ clock output from ENET_TD2 pin for phy?

Question asked by 念祖 姚 on Dec 6, 2018
Latest reply on Dec 6, 2018 by igorpadykov

Hello everybody:

 

I  have a custom  board  based on   IMX8MQ, and  a Micrel  KSZ8863  phy connect  to  IMX8MQ   in  rmii mode,and   KSZ8863 's   RMII_CLKIN   is connected to   IMX8MQ's   ENET_TD2 pin!    How can  I   enable 50M HZ   references  clock  output from ENET_TD2  for KSZ8863!

 

 

 

In  my  dts file     fsl-imx8mq-evk.dts, I modified it like  this:

 

191 pinctrl_fec1: fec1grp {
192    fsl,pins = <
211       MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
212       MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
213       MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f
214       /*MX8MQ_IOMUXC_ENET_TD2_ENET1_REF_CLK_ROOT 0x4000001f*/
215       /*MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x19 Set as gpio to test hardware!!!*/
216       MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56
217       MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56
218       MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56
219       MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56
220       MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56
221       MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56
222       MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56
224       >;
225    };

 

 

455 &fec1 {
456    pinctrl-names = "default";
457    pinctrl-0 = <&pinctrl_fec1>;
458    /*phy-mode = "rgmii-id"; yaonz */
459    phy-mode = "rmii";
460    fsl,magic-packet;
461
462    assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
463    <&clk IMX8MQ_SYS2_PLL_100M>,
464   <&clk IMX8MQ_SYS2_PLL_50M>;
465    assigned-clock-rates = <0>, <0>, <50000000>, <100000000>;
466    /*
467    */
468
469    phy-handle = <&ethphy0>;
470    status = "okay";
471 /*
472 */
474    mdio {
475          #address-cells = <1>;
476          #size-cells = <0>;
477
478          ethphy0: ethernet-phy@0 {
479                   compatible = "ethernet-phy-ieee802.3-c22";
480                     reg = <1>;
481                      /*
482                      at803x,led-act-blind-workaround;
483                      at803x,eee-disabled;
484                      */
485                };
486          };
487 };

And in  my  dtsi  file  fsl-imx8mq.dtsi , I modified it like  this:

1113 fec1: ethernet@30be0000 {
1114    compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1115    reg = <0x0 0x30be0000 0x0 0x10000>;
1116    interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1117    <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1118    <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1119    clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
1120    <&clk IMX8MQ_CLK_ENET1_ROOT>,
1121    <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
1122    <&clk IMX8MQ_CLK_ENET_REF_DIV>,
1123    /*<&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;*/
1124    <&clk IMX8MQ_CLK_ENET1_ROOT>;
1125    /*<&clk IMX8MQ_CLK_ENET_PHY_REF_SRC>;*/
1126
1127    clock-names = "ipg", "ahb", "ptp",
1128    "enet_clk_ref", "enet_out";
1129    assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
1130    <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
1131    <&clk IMX8MQ_CLK_ENET_REF_SRC>,
1132    <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
1133    assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1134    <&clk IMX8MQ_SYS2_PLL_100M>,
1135    <&clk IMX8MQ_SYS2_PLL_125M>;
1136    assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
1137    stop-mode = <&gpr 0x10 3>;
1138    fsl,num-tx-queues=<3>;
1139    fsl,num-rx-queues=<3>;
1140    fsl,wakeup_irq = <2>;
1141    status = "disabled";
1142 };

 

 

 

And I    finally   get  a  2.5MHZ  and  300mv   clock out  form   ENET_TD2   pin, which  is not i wanted!!!

 

 

Has  anyone encountered this problem?     How to  config   the  DTS  to enable   50MHZ    ENET_REF_CLK1  output from ENET_TD2 

 

 

 

ThankYou  Very Much!!!

 

 

  Junior Yao

  982586047@qq.com

 

 

 

 

 

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