AnsweredAssumed Answered

MPC8270 FCC (Ethernet) Frame Corruption Problem

Question asked by Muhammad Umer Saeed on Dec 2, 2018
Latest reply on Dec 11, 2018 by alexander.yakovlev

I am porting VxWorks on MPC8270 based board. I am running the board with following clock configurations.

 

Custom Board (Which has FCCs problem):
Processor: MPC8270 (3K49M, HiP7)
Clocks: 100MHz oscillator, 100MHz bus frequency, 250 MHz CPM frequency and 400MHz core clock
Reference Board (FCCs are working fine):
Processor: MPC8270 (3K49M, HiP7)
Clocks: 64MHz oscillator, 64MHz bus frequency, 192 MHz CPM frequency and 384MHz core clock

 

Problem:
When I am running the Ethernet on FCC (1, 2, 3) the frame is corrupted by the CPM (communication processor module). Communication processor module is corrupting the frame when reading from Tx buffers (Note: Data is correctly placed in the Tx buffers which I have verified by debugging the driver) which are placed in 60x Bus (SDRAM). CPM reads data in a corrupted manner and append padding and checksum to frame. On the host end I am running Wireshark to see the packets (Corrupted packets). I have debugged the hardware and software driver (Both seems good).

 

I have also a reference board running the same driver (working fine). The only difference between the custom board and the reference board is the clocks as mentioned above.

 

Does clocks makes difference to CPM module working? Is there a limit of setting clocks of CPM module? What are the possible outcomes of changing the clocks of CPM on the FCCs driver?

For detailed behavior of FCCs, attached is the file.

Attachments

Outcomes